BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
Ando, Kota, Ueyoshi, Kodai, Orimo, Kentaro, Yonekawa, Haruyoshi, Sato, Shimpei, Nakahara, Hiroki, Takamaeda-Yamazaki, Shinya, Ikebe, Masayuki, Asai, Tetsuya, Kuroda, Tadahiro, Motomura, Masato
Published in IEEE journal of solid-state circuits (01.04.2018)
Published in IEEE journal of solid-state circuits (01.04.2018)
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Journal Article
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS
Ueyoshi, Kodai, Ando, Kota, Hirose, Kazutoshi, Takamaeda-Yamazaki, Shinya, Hamada, Mototsugu, Kuroda, Tadahiro, Motomura, Masato
Published in IEEE journal of solid-state circuits (01.01.2019)
Published in IEEE journal of solid-state circuits (01.01.2019)
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Journal Article
Low-Power and ppm-Level Multimolecule Detection by Integration of Self-Heated Metal Nanosheet Sensors
Tanaka, Takahisa, Yanagida, Takeshi, Uchida, Ken, Tabuchi, Kenta, Tatehora, Kohei, Shiiki, Yohsuke, Nakagawa, Shuya, Takahashi, Tsunaki, Shimizu, Ryota, Ishikuro, Hiroki, Kuroda, Tadahiro
Published in IEEE transactions on electron devices (01.12.2019)
Published in IEEE transactions on electron devices (01.12.2019)
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Journal Article
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
Ueyoshi, Kodai, Ando, Kota, Hirose, Kazutoshi, Takamaeda-Yamazaki, Shinya, Kadomoto, Junichiro, Miyata, Tomoki, Hamada, Mototsugu, Kuroda, Tadahiro, Motomura, Masato
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion
Kosuge, Atsutake, Yu, Lixing, Hamada, Mototsugu, Matsuo, Kazuki, Kuroda, Tadahiro
Published in IEEE open journal of the Industrial Electronics Society (01.01.2023)
Published in IEEE open journal of the Industrial Electronics Society (01.01.2023)
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Journal Article
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
Li, Dongzhu, Hsu, Yao-Chung, Sumikawa, Rei, Kosuge, Atsutake, Hamada, Mototsugu, Kuroda, Tadahiro
Published in 2023 IEEE International Symposium on Circuits and Systems (ISCAS) (01.01.2023)
Published in 2023 IEEE International Symposium on Circuits and Systems (ISCAS) (01.01.2023)
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Conference Proceeding
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler
Kosuge, Atsutake, Mizuhara, Wataru, Shidei, Tsunaaki, Takeya, Tsutomu, Miura, Noriyuki, Taguchi, Masao, Ishikuro, Hiroki, Kuroda, Tadahiro
Published in IEEE journal of solid-state circuits (01.01.2014)
Published in IEEE journal of solid-state circuits (01.01.2014)
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Journal Article
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
Saito, Mitsuko, Yoshida, Yoichi, Miura, Noriyuki, Ishikuro, Hiroki, Kuroda, Tadahiro
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2010)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2010)
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Journal Article
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration
Niitsu, Kiichi, Sugimori, Yasufumi, Kohama, Yoshinori, Osada, Kenichi, Irie, Naohiko, Ishikuro, Hiroki, Kuroda, Tadahiro
Published in IEEE transactions on very large scale integration (VLSI) systems (01.10.2011)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.10.2011)
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Journal Article
Asynchronous Pulse Transmitter for Power Reduction in Inductive-Coupling Link
Saito, Mitsuko, Miura, Noriyuki, Kuroda, Tadahiro
Published in Japanese Journal of Applied Physics (01.02.2012)
Published in Japanese Journal of Applied Physics (01.02.2012)
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Journal Article
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
Niitsu, K., Kawai, S., Miura, N., Ishikuro, H., Kuroda, T.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2012)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2012)
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Journal Article
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
Saen, M., Osada, K., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., Kuroda, T.
Published in IEEE journal of solid-state circuits (01.04.2010)
Published in IEEE journal of solid-state circuits (01.04.2010)
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Journal Article
Conference Proceeding