An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS
Yoshioka, Kentaro, Shikata, Akira, Sekimoto, Ryota, Kuroda, Tadahiro, Ishikuro, Hiroki
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2015)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2015)
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Journal Article
Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions
Li, Dongzhu, Zhao, Tianqi, Kobayashi, Kenji, Kosuge, Atsutake, Hamada, Mototsugu, Kuroda, Tadahiro
Published in 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (19.05.2024)
Published in 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (19.05.2024)
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Conference Proceeding
1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller
Tomita, K., Shinoda, R., Kuroda, T., Ishikuro, H.
Published in IEEE journal of solid-state circuits (01.11.2012)
Published in IEEE journal of solid-state circuits (01.11.2012)
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Journal Article
Conference Proceeding
A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC
Shiba, Kota, Zhan, Zhijie, Nii, Koji, Wang, Yih, Chang, Tsung-Yung Jonathan, Kosuge, Atsutake, Hamada, Mototsugu, Kuroda, Tadahiro
Published in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) (09.09.2024)
Published in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) (09.09.2024)
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Conference Proceeding
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories
Kosuge, Atsutake, Hashiba, Junki, Kawajiri, Toru, Hasegawa, So, Shidei, Tsunaaki, Ishikuro, Hiroki, Kuroda, Tadahiro, Takeuchi, Ken
Published in IEEE journal of solid-state circuits (01.04.2016)
Published in IEEE journal of solid-state circuits (01.04.2016)
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Journal Article
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
Kagami, Takahiro, Matsutani, Hiroki, Koibuchi, Michihiro, Take, Yasuhiro, Kuroda, Tadahiro, Amano, Hideharu
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2016)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2016)
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Journal Article
Analytical thruchip inductive coupling channel design optimization
Li-Chung Hsu, Kadomoto, Junichiro, Hasegawa, So, Kosuge, Atsutake, Take, Yasuhiro, Kuroda, Tadahiro
Published in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2016)
Published in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2016)
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Conference Proceeding
Journal Article
A183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
Sumikawa, Rei, Kosuge, Atsutake, Hsu, Yao-Chung, Shiba, Kota, Hamada, Mototsugu, Kuroda, Tadahiro
Published in IEEE solid-state circuits letters (01.01.2024)
Published in IEEE solid-state circuits letters (01.01.2024)
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Journal Article
Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation
Maruyama, Tsuyoshi, Hamada, Mototsugu, Kuroda, Tadahiro
Published in 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2018)
Published in 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2018)
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Conference Proceeding
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
Kosuge, Atsutake, Sumikawa, Rei, Hsu, Yao-Chung, Shiba, Kota, Hamada, Mototsugu, Kuroda, Tadahiro
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
Published in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (11.06.2023)
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Conference Proceeding