Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield
Sakui, Koji, Li, Yisuo, Kakumu, Masakazu, Kanazawa, Kenichi, Kunishima, Iwao, Iwata, Yoshihisa, Harada, Nozomu
Published in Memories - Materials, Devices, Circuits and Systems (01.07.2023)
Published in Memories - Materials, Devices, Circuits and Systems (01.07.2023)
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Journal Article
RESISTANCE CHANGE TYPE MEMORY
NOMURA YUKIHIRO, KAMATA YOSHIKI, KUNISHIMA IWAO, ASAO YOSHIAKI, MOROTA MISAKO
Year of Publication 24.09.2020
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Year of Publication 24.09.2020
Patent
NONVOLATILE STORAGE AND METHOD FOR MANUFACTURING THE SAME
NOMURA YUKIHIRO, KAMATA YOSHIKI, KUNISHIMA IWAO, ASAO YOSHIAKI, MOROTA MISAKO
Year of Publication 26.09.2019
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Year of Publication 26.09.2019
Patent
Homogeneous heteroepitaxial NiSi2 formation on (100)Si
KUNISHIMA, I, SUGURO, K, AOYAMA, T, MATSUNAGA, J
Published in Japanese journal of applied physics (01.12.1990)
Published in Japanese journal of applied physics (01.12.1990)
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Journal Article
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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Journal Article
Conference Proceeding
Anomalous junction leakage behavior of Ti self aligned silicide contacts on ultra-shallow junctions
SAKATA, A, TOMITA, M, KOIKE, M, KOYAMA, M, KUNISHIMA, I
Published in Japanese Journal of Applied Physics (01.03.1997)
Published in Japanese Journal of Applied Physics (01.03.1997)
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Conference Proceeding
Journal Article
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
Hoya, Katsuhiko, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, S M, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A, Fujii, S
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
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Journal Article
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs
Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A.
Published in IEEE journal of solid-state circuits (01.09.2011)
Published in IEEE journal of solid-state circuits (01.09.2011)
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Journal Article
Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI
Morimoto, T., Ohguro, T., Momose, S., Iinuma, T., Kunishima, I., Suguro, K., Katakabe, I., Nakajima, H., Tsuchiaki, M., Ono, M., Katsumata, Y., Iwai, H.
Published in IEEE transactions on electron devices (01.05.1995)
Published in IEEE transactions on electron devices (01.05.1995)
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Journal Article