A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
Matano, T., Takai, Y., Takahashi, T., Sakito, Y., Fujii, I., Takaishi, Y., Fujisawa, H., Kubouchi, S., Narui, S., Arai, K., Morino, M., Nakamura, M., Miyatake, S., Sekiguchi, T., Koyama, K.
Published in IEEE journal of solid-state circuits (01.05.2003)
Published in IEEE journal of solid-state circuits (01.05.2003)
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Journal Article
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme
Fujisawa, H., Kubouchi, S., Kuroki, K., Nishioka, N., Riho, Y., Noda, H., Fujii, I., Yoko, H., Takishita, R., Ito, T., Tanaka, H., Nakamura, M.
Published in IEEE journal of solid-state circuits (01.01.2007)
Published in IEEE journal of solid-state circuits (01.01.2007)
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Journal Article
Conference Proceeding
1.8-v 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1-Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer
FUJISAWA, Hiroki, NAKAMURA, Masayuki, ARAI, Koji, KUBOUCHI, Shuichi, FUJII, Isamu, YOKO, Hideyuki, ADACHI, Takao, TAKAI, Yasuhiro, KOSHIKAWA, Yasuji, MATANO, Tatsuya, NARUI, Seiji, USUKI, Narikazu, DONO, Chiaki, MIYATAKE, Shinichi, MORINO, Makoto
Published in IEEE journal of solid-state circuits (01.04.2005)
Published in IEEE journal of solid-state circuits (01.04.2005)
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Conference Proceeding