A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
Takai, Y., Fujita, M., Nagata, K., Isa, S., Nakazawa, S., Hirobe, A., Ohkubo, H., Sakao, M., Horiba, S., Fukase, T., Takaishi, Y., Matsuo, M., Komuro, M., Uchida, T., Sakoh, T., Saino, K., Uchiyama, S., Takada, Y., Sekine, J., Nakanishi, N., Oikawa, T., Igeta, M., Tanabe, H., Miyamoto, H., Hashimoto, T., Yamaguchi, H., Koyama, K., Kobayashi, Y., Okuda, T.
Published in IEEE journal of solid-state circuits (01.02.2000)
Published in IEEE journal of solid-state circuits (01.02.2000)
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