A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
Barth, J., Reohr, W.R., Parries, P., Fredeman, G., Golz, J., Schuster, S.E., Matick, R.E., Hunter, H., Tanner, C.C., Harig, J., Kim Hoki, Khan, B.A., Griesemer, J., Havreluk, R.P., Yanagisawa, K., Kirihata, T., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.01.2008)
Published in IEEE journal of solid-state circuits (01.01.2008)
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
Klim, P.J., Barth, J., Reohr, W.R., Dick, D., Fredeman, G., Koch, G., Le, H.M., Khargonekar, A., Wilcox, P., Golz, J., Kuang, J.B., Mathews, A., Law, J.C., Luong, T., Ngo, H.C., Freese, R., Hunter, H.C., Nelson, E., Parries, P., Kirihata, T., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
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An 800-MHz embedded DRAM with a concurrent refresh mode
Kirihata, T., Parries, P., Hanson, D.R., Hoki Kim, Golz, J., Fredeman, G., Rajeevakumar, R., Griesemer, J., Robson, N., Cestero, A., Khan, B.A., Geng Wang, Wordeman, M., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.06.2005)
Published in IEEE journal of solid-state circuits (01.06.2005)
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Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM
Rosenblatt, S., Fainstein, D., Cestero, A., Safran, J., Robson, N., Kirihata, T., Iyer, S. S.
Published in IEEE journal of solid-state circuits (01.04.2013)
Published in IEEE journal of solid-state circuits (01.04.2013)
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Fault-tolerant designs for 256 Mb DRAM
Kirihata, T., Watanabe, Y., Hing Wong, DeBrosse, J.K., Yoshida, M., Kato, D., Fujii, S., Wordeman, M.R., Poechmueller, P., Parke, S.A., Asao, Y.
Published in IEEE journal of solid-state circuits (01.04.1996)
Published in IEEE journal of solid-state circuits (01.04.1996)
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Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond
Khan, F., Moy, D., Anand, D., Schroeder, E.H., Katz, R., Jiang, L., Banghart, E., Robson, N., Kirihata, T.
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Flexible test mode approach for 256-Mb DRAM
Kirihata, T., Hing Wong, DeBrosse, J.K., Watanabe, Y., Hara, T., Yoshida, M., Wordeman, M.R., Fujii, S., Asao, Y., Krsnik, B.
Published in IEEE journal of solid-state circuits (01.10.1997)
Published in IEEE journal of solid-state circuits (01.10.1997)
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Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
Kothandaraman, C., Chen, X., Moy, D., Lea, D., Rosenblatt, S., Khan, F., Leu, D., Kirihata, T., Ioannou, D., LaRosa, G., Johnson, J. B., Robson, N., Iyer, S. S.
Published in 2015 IEEE International Reliability Physics Symposium (01.04.2015)
Published in 2015 IEEE International Reliability Physics Symposium (01.04.2015)
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MTPM ramped programming optimization methodology
Randriamihaja, Y. Mamy, McMahon, W., Kerber, A., Chbili, Z., Parameshwaran, B., Kirihata, T., Cestero, A., Robson, N., Moy, D., Katz, R., Anand, D., Pape, J., Iyer, S. S.
Published in 2017 IEEE International Reliability Physics Symposium (IRPS) (01.04.2017)
Published in 2017 IEEE International Reliability Physics Symposium (IRPS) (01.04.2017)
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Three Dimensional integration - Considerations for memory applications
Iyer, S. S., Kirihata, T., Barth, J. E.
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
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Conformation and the sodium ion condensation on DNA and RNA structures in the presence of a neutral cosolute as a mimic of the intracellular media
Nakano, Shu-Ichi, Wu, Lei, Oka, Hirohito, Karimata, Hisae Tateishi, Kirihata, Toshimasa, Sato, Yuichi, Fujii, Satoshi, Sakai, Hiroshi, Kuwahara, Masayasu, Kuwahara, Masayuki, Sawai, Hiroaki, Sugimoto, Naoki
Published in Molecular bioSystems (01.01.2008)
Published in Molecular bioSystems (01.01.2008)
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A 14-ns 14-Mb CMOS DRAM with 300-mW active power
Kirihata, T., Dhong, S.H., Kitamura, K., Sunaga, T., Katayama, Y., Scheuerlein, R.E., Satoh, A., Sakaue, Y., Tobimatsu, K., Hosokawa, K., Saitoh, T., Yoshikawa, T., Hashimoto, H., Kazusawa, M.
Published in IEEE journal of solid-state circuits (01.09.1992)
Published in IEEE journal of solid-state circuits (01.09.1992)
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A pulsed sensing scheme with a limited bit-line swing
Scheuerlein, R.E., Katayama, Y., Kirihata, T., Sakaue, Y., Satoh, A., Sunaga, T., Yoshikawa, T., Kitamura, K., Dhong, S.H.
Published in IEEE journal of solid-state circuits (01.04.1992)
Published in IEEE journal of solid-state circuits (01.04.1992)
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Evaluation of combustion characteristics of low grade bunker fuel by flame of single droplet
"Morishita, S. (Shimonoseki Univ. of Fisheries, Yamaguchi (Japan)), Maeda, K, Abe, S, Tsuda, M, Kirihata, T.
Published in Journal of the Shimonoseki University of Fisheries (Japan) (01.04.2002)
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Published in Journal of the Shimonoseki University of Fisheries (Japan) (01.04.2002)
Journal Article
Process-design considerations for three dimensional memory integration
Iyer, S.S., Kirihata, T., Wordeman, M.R., Barth, J., Hannon, R.H., Malik, R.
Published in 2009 Symposium on VLSI Technology (01.06.2009)
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Published in 2009 Symposium on VLSI Technology (01.06.2009)
Conference Proceeding
Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications
Ji, B.L., Munetoh, S., Chorng-Lii Hwang, Wordeman, M., Kirihata, T.
Published in 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) (2003)
Published in 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) (2003)
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A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing
Lu, N.C.-C., Bronner, G.B., Kitamura, K., Scheuerlein, R.E., Henkels, W.H., Dhong, S.H., Katayama, Y., Kirihata, T., Niijima, H., Franch, R.L., Wang, W., Nishiwaki, M., Pesavento, F.L., Rajeevakumar, T.V., Sakaue, Y., Suzuki, Y., Iguchi, Y., Yano, E.
Published in IEEE journal of solid-state circuits (01.10.1989)
Published in IEEE journal of solid-state circuits (01.10.1989)
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Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
Robson, N., Safran, J., Kothandaraman, C., Cestero, A., Xiang Chen, Rajeevakumar, R., Leslie, A., Moy, D., Kirihata, T., Iyer, S.
Published in 2007 IEEE Custom Integrated Circuits Conference (01.09.2007)
Published in 2007 IEEE Custom Integrated Circuits Conference (01.09.2007)
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