All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
Seong, Kihwan, Lee, Won-Cheol, Kim, Byungsub, Sim, Jae-Yoon, Park, Hong-June
Published in Journal of semiconductor technology and science (2016)
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Published in Journal of semiconductor technology and science (2016)
Journal Article
5.7 A 29nW bandgap reference circuit
Lee, Jong Mi, Ji, Youngwoo, Choi, Seungnam, Cho, Young-Chul, Jang, Seong-Jin, Choi, Joo Sun, Kim, Byungsub, Park, Hong-June, Sim, Jae-Yoon
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
3 x 16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces
Moon, Changjae, Jang, Iksu, Lim, Sungmin, Huh, Yaejoon, Kim, Byungsub
Published in IEEE transactions on circuits and systems. II, Express briefs (08.08.2024)
Published in IEEE transactions on circuits and systems. II, Express briefs (08.08.2024)
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Journal Article
A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example
Kim, Kwangmin, Song, Hyoseok, Lee, Byeongcheol, Kim, Byungsub
Published in IEEE transactions on very large scale integration (VLSI) systems (01.05.2023)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.05.2023)
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Journal Article