Random Dopant Fluctuation in Limited-Width FinFET Technologies
CHIANG, Meng-Hsueh, LIN, Jeng-Nan, KIM, Keunwoo, CHUANG, Ching-Te
Published in IEEE transactions on electron devices (01.08.2007)
Published in IEEE transactions on electron devices (01.08.2007)
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Journal Article
High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices
Chiang, M.-H., Kim, K., Chuang, C.-T., Tretz, C.
Published in IEEE transactions on electron devices (01.09.2006)
Published in IEEE transactions on electron devices (01.09.2006)
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Journal Article
TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability
Keunwoo Kim, Kuang, J.B., Gebara, F.H., Ngo, H.C., Ching-Te Chuang, Nowka, K.J.
Published in IEEE transactions on electron devices (01.12.2009)
Published in IEEE transactions on electron devices (01.12.2009)
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Journal Article
Leakage power analysis of 25-nm double-gate CMOS devices and circuits
Keunwoo Kim, Das, K.K., Joshi, R.V., Ching-Te Chuang
Published in IEEE transactions on electron devices (01.05.2005)
Published in IEEE transactions on electron devices (01.05.2005)
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Journal Article
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction
Joshi, Rajiv V., Keunwoo Kim, Kanj, Rouwaida, Bhoj, Ajay N., Ziegler, Matthew M., Oldiges, Phil, Kerber, Pranita, Wong, Robert, Hook, Terence, Saroop, Sudesh, Radens, Carl, Chun-Chen Yeh
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2015)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2015)
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Journal Article
Novel high-density low-power logic circuit techniques using DG devices
Meng-Hsueh Chiang, Keunwoo Kim, Tretz, C., Ching-Te Chuang
Published in IEEE transactions on electron devices (01.10.2005)
Published in IEEE transactions on electron devices (01.10.2005)
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Journal Article
Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications
CHIANG, Meng-Hsueh, LIN, Jeng-Nan, KIM, Keunwoo, CHUANG, Ching-Te
Published in IEEE transactions on electron devices (01.09.2008)
Published in IEEE transactions on electron devices (01.09.2008)
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Journal Article
The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology
Deng, Jie, Kim, Keunwoo, Chuang, Ching-Te, Wong, H.-S. Philip
Published in IEEE transactions on electron devices (01.05.2007)
Published in IEEE transactions on electron devices (01.05.2007)
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Journal Article
Turning silicon on its edge [double gate CMOS/FinFET technology]
Nowak, E.J., Aller, I., Ludwig, T., Kim, K., Joshi, R.V., Ching-Te Chuang, Bernstein, K., Puri, R.
Published in IEEE circuits and devices magazine (01.01.2004)
Published in IEEE circuits and devices magazine (01.01.2004)
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Journal Article
Optimal Dual-[Formula Omitted] Design in Sub-100-nm PD/SOI and Double-Gate Technologies
Bansal, A, Kim, Jae-Joon, Kim, Keunwoo, Mukhopadhyay, S, Chuang, Ching-Te, Roy, K
Published in IEEE transactions on electron devices (01.05.2008)
Published in IEEE transactions on electron devices (01.05.2008)
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Journal Article
Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate
Keunwoo Kim, Hanafi, H.I., Jin Cai, Ching-Te Chuang
Published in IEEE transactions on electron devices (01.09.2005)
Published in IEEE transactions on electron devices (01.09.2005)
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Journal Article