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Year of Publication 25.08.2011
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Year of Publication 01.06.1998
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A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process
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DATA-TRASMISSION CIRCUIT, DATA-LINE DRIVING CIRCUIT, AMPLIFYING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY
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Year of Publication 29.04.1998
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0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability
Kikukawa, H., Tomishima, S., Tsuji, T., Kawasaki, T., Sakamoto, S., Ishikawa, M., Abe, W., Tanizaki, H., Kato, H., Uchikoba, T., Inokuchi, T., Senoh, M., Fukushima, Y., Nirro, M., Maruta, M., Shibayama, A., Ooishi, T., Takahashi, K., Hidaka, H.
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A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications
Tomishima, S., Tsuji, T., Kawasaki, T., Ishikawa, M., Inokuchi, T., Kato, H., Tanizaki, H., Abe, W., Shibayama, A., Fukushima, Y., Niiro, M., Maruta, M., Uchikoba, T., Senoh, M., Sakamoto, S., Ooishi, T., Kikukawa, H., Hidaka, H., Takahashi, K.
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Year of Publication 13.10.2011
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Year of Publication 13.10.2011
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NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC APPARATUS
KOUNO KAZUYUKI, MISHIMA SATOSHI, TOKI MASAHIRO, KIKUKAWA HIROHITO, MUKUNOKI TOSHIO, SUGIMOTO AKIRA
Year of Publication 25.10.2012
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Year of Publication 25.10.2012
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