Demonstration of 90 000 superconductive bump connections for massive quantum computing
Araga, Yuuki, Nakagawa, Hiroshi, Hashino, Masaru, Kikuchi, Katsuya
Published in Japanese Journal of Applied Physics (01.04.2023)
Published in Japanese Journal of Applied Physics (01.04.2023)
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Journal Article
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices
Miki, Takuji, Nagata, Makoto, Sonoda, Hiroki, Miura, Noriyuki, Okidono, Takaaki, Araga, Yuuki, Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya
Published in IEEE journal of solid-state circuits (01.10.2020)
Published in IEEE journal of solid-state circuits (01.10.2020)
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Journal Article
Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation
Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya
Published in Japanese Journal of Applied Physics (01.07.2018)
Published in Japanese Journal of Applied Physics (01.07.2018)
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Journal Article
Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias
Araga, Yuuki, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (01.04.2018)
Published in Japanese Journal of Applied Physics (01.04.2018)
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Journal Article
Validation of TSV thermo-mechanical simulation by stress measurement
Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya
Published in Microelectronics and reliability (01.04.2016)
Published in Microelectronics and reliability (01.04.2016)
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Journal Article
Fabrication and stress analysis of annular-trench-isolated TSV
Feng, Wei, Bui, Tung Thanh, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya
Published in Microelectronics and reliability (01.08.2016)
Published in Microelectronics and reliability (01.08.2016)
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Journal Article
Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer
Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio
Published in Japanese Journal of Applied Physics (01.06.2019)
Published in Japanese Journal of Applied Physics (01.06.2019)
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Journal Article
Investigation of transient thermal dissipation in thinned LSI for advanced packaging
Araga, Yuuki, Shimamoto, Haruo, Melamed, Samson, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (01.04.2018)
Published in Japanese Journal of Applied Physics (01.04.2018)
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Journal Article
Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer
Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio
Published in Japanese Journal of Applied Physics (01.07.2017)
Published in Japanese Journal of Applied Physics (01.07.2017)
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Journal Article
Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration
Araga, Yuuki, Nagata, Makoto, Miura, Noriyuki, Ikeda, Hiroaki, Kikuchi, Katsuya
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.02.2018)
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.02.2018)
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Journal Article
Three-dimensional integration technology of magnetic tunnel junctions for magnetoresistive random access memory application
Yakushiji, Kay, Takagi, Hideki, Watanabe, Naoya, Fukushima, Akio, Kikuchi, Katsuya, Kurashima, Yuuichi, Sugihara, Atsushi, Kubota, Hitoshi, Yuasa, Shinji
Published in Applied physics express (01.06.2017)
Published in Applied physics express (01.06.2017)
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Journal Article
Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits
Melamed, Samson, Imura, Fumito, Nakagawa, Hiroshi, Kikuchi, Katsuya, Hagimoto, Michiya, Matsumoto, Yukoh, Aoyagi, Masahiro
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.03.2019)
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.03.2019)
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Journal Article
Hardness Characteristics of Au Cone-Shaped Bumps Targeted for 3-D Packaging Applications
Lim, Ying Ying, Nakagawa, Hiroshi, Hashino, Masaru, Aoyagi, Masahiro, Kikuchi, Katsuya
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.03.2019)
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.03.2019)
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Journal Article
A method enabling height-control of chips for edge-emitting laser stacking
Tung, Bui Thanh, Ma, Laina, Amano, Takeru, Kikuchi, Katsuya, Mori, Masahiko, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (01.04.2015)
Published in Japanese Journal of Applied Physics (01.04.2015)
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Journal Article
EMI performance of power delivery networks in 3D TSV integration
Araga, Yuuki, Nagata, Makoto, Miura, Noriyuki, Ikeda, Hiroaki, Kikuchi, Katsuya
Published in 2016 International Symposium on Electromagnetic Compatibility - EMC EUROPE (01.09.2016)
Published in 2016 International Symposium on Electromagnetic Compatibility - EMC EUROPE (01.09.2016)
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Conference Proceeding
15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications
Tung, Bui Thanh, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (17.03.2014)
Published in Japanese Journal of Applied Physics (17.03.2014)
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Journal Article