Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
Minki Cho, Kim, Stephen T., Tokunaga, Carlos, Augustine, Charles, Kulkarni, Jaydeep P., Ravichandran, Krishnan, Tschanz, James W., Khellah, Muhammad M., De, Vivek
Published in IEEE journal of solid-state circuits (01.01.2017)
Published in IEEE journal of solid-state circuits (01.01.2017)
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Journal Article
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS
Jain, Rinkle, Geuskens, Bibiche M., Kim, Stephen T., Khellah, Muhammad M., Kulkarni, Jaydeep, Tschanz, James W., De, Vivek
Published in IEEE journal of solid-state circuits (01.04.2014)
Published in IEEE journal of solid-state circuits (01.04.2014)
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Journal Article
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator
Kim, Stephen T., Yi-Chun Shih, Mazumdar, Kaushik, Jain, Rinkle, Ryan, Joseph F., Tokunaga, Carlos, Augustine, Charles, Kulkarni, Jaydeep P., Ravichandran, Krishnan, Tschanz, James W., Khellah, Muhammad M., De, Vivek
Published in IEEE journal of solid-state circuits (01.01.2016)
Published in IEEE journal of solid-state circuits (01.01.2016)
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Journal Article
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
Bowman, K A, Tschanz, J W, Lu, S L, Aseron, P A, Khellah, M M, Raychowdhury, A, Geuskens, B M, Tokunaga, C, Wilkerson, C B, Karnik, T, De, V K
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Journal Article
Conference Proceeding
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization
Meinerzhagen, Pascal A., Tokunaga, Carlos, Malavasi, Andres, Vaidya, Vaibhav, Mendon, Ashwin, Mathaikutty, D., Kulkarni, Jaydeep, Augustine, Charles, Cho, Minki, Kim, Stephen T., Matthew, George E., Jain, Rinkle, Ryan, Joseph, Peng, Chung-Ching, Paul, Somnath, Vangal, Sriram, Perez Esparza, Brando, Cuellar, L., Woodman, M., Iyer, Bala, Maiyuran, Subramaniam, Chinya, G., Zou, Xiang, Liao, Yuyun, Ravichandran, Krishnan, Wang, H., Khellah, Muhammad M., Tschanz, James W., De, Vivek
Published in IEEE journal of solid-state circuits (01.01.2019)
Published in IEEE journal of solid-state circuits (01.01.2019)
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Journal Article
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS
Bang, Suyoung, Lim, Wootaek, Augustine, Charles, Malavasi, Andres, Khellah, Muhammad, Tschanz, James, De, Vivek
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS
Meinerzhagen, Pascal A., Kundu, Sandip, Malavasi, Andres, Nguyen, Trang, Khellah, Muhammad M., Tschanz, James W., De, Vivek
Published in IEEE solid-state circuits letters (01.09.2019)
Published in IEEE solid-state circuits letters (01.09.2019)
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Journal Article
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS
Meinerzhagen, Pascal A., Kundu, Sandip, Malavasi, Andres, Nguyen, Trang, Khellah, Muhammad M., Tschanz, James W., De, Vivek
Published in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) (01.09.2019)
Published in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) (01.09.2019)
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Conference Proceeding
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology
Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.
Published in IEEE journal of solid-state circuits (01.01.2009)
Published in IEEE journal of solid-state circuits (01.01.2009)
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Journal Article
Conference Proceeding
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS
Minki Cho, Tokunaga, Carlos, Khellah, Muhammad M., Tschanz, James W., De, Vivek
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
Published in 2015 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2015)
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Conference Proceeding
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays
Raychowdhury, Arijit, Geuskens, Bibiche M, Bowman, Keith A, Tschanz, James W, Lu, Shih-Lien L, Karnik, Tanay, Khellah, Muhammad M, De, Vivek K
Published in IEEE journal of solid-state circuits (01.04.2011)
Published in IEEE journal of solid-state circuits (01.04.2011)
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Journal Article
Conference Proceeding
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control
Bowman, K. A., Tokunaga, C., Tschanz, J. W., Raychowdhury, A., Khellah, M. M., Geuskens, B. M., Lu, Shih-Lien L., Aseron, P. A., Karnik, T., De, V. K.
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2011)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2011)
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Journal Article
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation
Kim, Stephen T., Yi-Chun Shih, Mazumdar, Kaushik, Jain, Rinkle, Ryan, Joseph F., Tokunaga, Carlos, Augustine, Charles, Kulkarni, Jaydeep P., Ravichandran, Krishnan, Tschanz, James W., Khellah, Muhammad M., De, Vivek
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
Raychowdhury, A., Geuskens, B., Kulkarni, J., Tschanz, J., Bowman, K., Karnik, T., Shih-Lien Lu, De, V., Khellah, M.M.
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling
Azizi, N., Khellah, M.M., De, V.K., Najm, F.N.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2007)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2007)
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Journal Article
Advances in Microprocessor Cache Architectures Over the Last 25 Years
Iyer, Ravi, De, Vivek, Illikkal, Ramesh, Koufaty, David, Chitlur, Bhushan, Herdrich, Andrew, Khellah, Muhammad, Hamzaoglu, Fatih, Karl, Eric
Published in IEEE MICRO (01.11.2021)
Published in IEEE MICRO (01.11.2021)
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Journal Article
Session 5 - Memory for emerging applications
Khellah, Muhammad, Joshi, Rajiv
Published in 2017 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2017)
Published in 2017 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2017)
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Conference Proceeding
An All-Digital, V} -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop
Bang, Suyoung, Cho, Minki, Meinerzhagen, Pascal A., Malavasi, Andres, Khellah, Muhammad M., Tschanz, James W., De, Vivek
Published in IEEE journal of solid-state circuits (01.07.2020)
Published in IEEE journal of solid-state circuits (01.07.2020)
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Journal Article