Search Results - "KER, Ming-Dou" :: K.UTB vyhledávací portál

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Latchup Risk in a 4H-SiC Process

by Ke, Chao-Yang, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.05.2024)

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Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-μm BCD Technology

by Hsu, Chen-Wei, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.03.2024)

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Design of Bi-Directional ESD Protection Circuit With Uni-Directional ESD Device in BCD Technology

by Hsu, Chen-Wei, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.10.2023)

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Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

by Hsieh, Chia-Chi, Ker, Ming-Dou
Published in IEEE transactions on biomedical circuits and systems (01.06.2021)

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Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

by Hsueh, Cheng-Yun, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.04.2021)

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Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

by Chang, Rong-Kun, Ker, Ming-Dou
Published in IEEE electron device letters (01.03.2021)

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Schottky-Embedded Silicon-Controlled Rectifier With High Holding Voltage Realized in a 0.18-μm Low-Voltage CMOS Process

by Chang, Rong-Kun, Peng, Bo-Wei, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.04.2021)

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The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

by Shen, Yu-Shu, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.05.2021)

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Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation

by Lin, Shiau-Pin, Ker, Ming-Dou
Published in IEEE transactions on circuits and systems. I, Regular papers (01.11.2020)

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The Parasitic Latch-Up Path From Substrate P⁺ Guard Ring to the NMOS in Deep N-Well Operating With Negative Voltage Sources

by Jiang, Zi-Hong, Ker, Ming-Dou
Published in IEEE electron device letters (01.04.2022)

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Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications

by Hsu, Chen-Wei, Li, Yu-Hsin, Ker, Ming-Dou
Published in IEEE transactions on electron devices (01.10.2022)

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A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

by Luo, Zhicong, Ker, Ming-Dou
Published in IEEE transactions on biomedical circuits and systems (01.12.2016)

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An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process

by Luo, Zhicong, Yu, Li-Chin, Ker, Ming-Dou
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2019)

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A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

by Cheng, Cheng-Hsiang, Tsai, Ping-Yuan, Yang, Tzu-Yi, Cheng, Wan-Hsueh, Yen, Ting-Yang, Luo, Zhicong, Qian, Xin-Hong, Chen, Zhi-Xin, Lin, Tzu-Han, Chen, Wei-Hong, Chen, Wei-Ming, Liang, Sheng-Fu, Shaw, Fu-Zen, Chang, Cheng-Siu, Hsin, Yue-Loong, Lee, Chen-Yi, Ker, Ming-Dou, Wu, Chung-Yu
Published in IEEE journal of solid-state circuits (01.11.2018)

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