Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors
Waidyasooriya, H. M., Ohbayashi, Y., Hariyama, M., Kameyama, M.
Published in IEEE transactions on circuits and systems for video technology (01.10.2011)
Published in IEEE transactions on circuits and systems for video technology (01.10.2011)
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Journal Article
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme
Harada, Shintaro, Xu Bai, Kameyama, Michitaka, Fujioka, Yoshichika
Published in 2014 IEEE 44th International Symposium on Multiple-Valued Logic (01.05.2014)
Published in 2014 IEEE 44th International Symposium on Multiple-Valued Logic (01.05.2014)
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Conference Proceeding
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation
Waidyasooriya, Hasitha Muthumala, Hariyama, Masanori, Takei, Yasuhiro, Kameyama, Michitaka
Published in Journal of Computational Engineering (04.12.2014)
Published in Journal of Computational Engineering (04.12.2014)
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Journal Article
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors
WAIDYASOORIYA, Hasitha Muthumala, OHBAYASHI, Yosuke, HARIYAMA, Masanori, KAMEYAMA, Michitaka
Published in IEICE Transactions on Information and Systems (2012)
Published in IEICE Transactions on Information and Systems (2012)
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Journal Article
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
ISHIHARA, Shota, IDOBATA, Noriaki, HARIYAMA, Masanori, KAMEYAMA, Michitaka
Published in IEICE Transactions on Information and Systems (2010)
Published in IEICE Transactions on Information and Systems (2010)
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Journal Article
Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs
Ishihara, Shota, Xia, Zhengfan, Hariyama, Masanori, Kameyama, Michitaka
Published in Journal of semiconductor technology and science (30.09.2010)
Published in Journal of semiconductor technology and science (30.09.2010)
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Journal Article
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit
Zhengfan Xia, Ishihara, S., Hariyama, M., Kameyama, M.
Published in 2012 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2012)
Published in 2012 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2012)
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Conference Proceeding
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals
Ishikawa, Akitaka, Okada, Nobuaki, Kameyama, Michitaka
Published in 2010 40th IEEE International Symposium on Multiple-Valued Logic (01.01.2010)
Published in 2010 40th IEEE International Symposium on Multiple-Valued Logic (01.01.2010)
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Conference Proceeding
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation
Lukac, Martin, Ben Shuai, Kameyama, Michitaka, Miller, D. Michael
Published in 2011 41st IEEE International Symposium on Multiple-Valued Logic (01.05.2011)
Published in 2011 41st IEEE International Symposium on Multiple-Valued Logic (01.05.2011)
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Conference Proceeding