RESISTANCE REDUCTION FOR WORD LINES IN MEMORY ARRAYS
SRINIVASAN PRASANNA, KANG SUNG TAEG, KALAVADE PRANAV, JUNGROTH OWEN W
Year of Publication 01.09.2021
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Year of Publication 01.09.2021
Patent
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
SRINIVASAN CHARAN, PARAT KRISHNA K, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 30.09.2019
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Year of Publication 30.09.2019
Patent
A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells
Torsi, A, Yijie Zhao, Haitao Liu, Tanzawa, T, Goda, A, Kalavade, P, Parat, K
Published in IEEE transactions on electron devices (01.01.2011)
Published in IEEE transactions on electron devices (01.01.2011)
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Journal Article
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-nand Technology and Featuring a 23.3 Gb/mm 2 Bit Density
Khakifirooz, Ali, Anaya, Eduardo, Balasubrahmanyam, Sriram, Bennett, Geoff, Castro, Daniel, Egler, John, Fan, Kuangchan, Ferdous, Rifat, Ganapathi, Kartik, Guzman, Omar, Ha, Chang Wan, Haque, Rezaul, Harish, Vinaya, Jalalifar, Majid, Jungroth, Owen W., Kang, Sung-Taeg, Karbasian, Golnaz, Kim, Jee-Yeon, Li, Siyue, Madraswala, Aliasgar S., Maddukuri, Srivijay, Mohammed, Amr, Mookiah, Shanmathi, Nagabhushan, Shashi, Ngo, Binh, Patel, Deep, Poosarla, Sai Kumar, Prabhu, Naveen V., Quiroga, Carlos, Rajwade, Shantanu, Rahman, Ahsanur, Shah, Jalpa, Shenoy, Rohit S., Menson, Ebenezer Tachie, Tankasala, Archana, Thirumala, Sandeep Krishna, Upadhyay, Sagar, Upadhyayula, Krishnasree, Velasco, Ashley, Vemula, Nanda Kishore Babu, Venkataramaiah, Bhaskar, Zhou, Jiantao, Pathak, Bharat M., Kalavade, Pranav
Published in IEEE solid-state circuits letters (2023)
Published in IEEE solid-state circuits letters (2023)
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Journal Article
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density
Khakifirooz, Ali, Anaya, Eduardo, Balasubrahrmanyam, Sriram, Bennett, Geoff, Castro, Daniel, Egler, John, Fan, Kuangchan, Ferdous, Rifat, Ganapathi, Kartik, Guzman, Omar, Ha, Chang Wan, Haque, Rezaul, Harish, Vinaya, Jalalifar, Majid, Jungroth, Owen W., Kang, Sung-Taeg, Karbasian, Golnaz, Kim, Jee-Yeon, Li, Siyue, Madraswala, Aliasgar S., Maddukuri, Srivijay, Mohammed, Amr, Mookiah, Shanmathi, Nagabhushan, Shashi, Ngo, Binh, Patel, Deep, Poosarla, Sai Kumar, Prabhu, Naveen V., Quiroga, Carlos, Rajwade, Shantanu, Rahman, Ahsanur, Shah, Jalpa, Shenoy, Rohit S., Menson, Ebenezer Tachie, Tankasala, Archana, Thirumala, Sandeep Krishna, Upadhyay, Sagar, Upadhyayula, Krishnasree, Velasco, Ashley, Vemula, Nanda Kishore Babu, Venkataramaiah, Bhaskar, Zhou, Jiantao, Pathak, Bharat M., Kalavade, Pranav
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
Published in 2023 IEEE International Solid- State Circuits Conference (ISSCC) (19.02.2023)
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Conference Proceeding
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
SRINIVASAN CHARAN, PARAT KRISHNA K, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 22.03.2017
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Year of Publication 22.03.2017
Patent
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3 Gb/mm2 Bit Density
Khakifirooz, Ali, Anaya, Eduardo, Balasubrahmanyam, Sriram, Bennett, Geoff, Castro, Daniel, Egler, John, Fan, Kuangchan, Ferdous, Rifat, Ganapathi, Kartik, Guzman, Omar, Ha, Chang Wan, Haque, Rezaul, Harish, Vinaya, Jalalifar, Majid, Jungroth, Owen W., Kang, Sung-Taeg, Karbasian, Golnaz, Kim, Jee-Yeon, Li, Siyue, Madraswala, Aliasgar S., Maddukuri, Srivijay, Mohammed, Amr, Mookiah, Shanmathi, Nagabhushan, Shashi, Ngo, Binh, Patel, Deep, Poosarla, Sai Kumar, Prabhu, Naveen V., Quiroga, Carlos, Rajwade, Shantanu, Rahman, Ahsanur, Shah, Jalpa, Shenoy, Rohit S., Menson, Ebenezer Tachie, Tankasala, Archana, Thirumala, Sandeep Krishna, Upadhyay, Sagar, Upadhyayula, Krishnasree, Velasco, Ashley, Vemula, Nanda Kishore Babu, Venkataramaiah, Bhaskar, Zhou, Jiantao, Pathak, Bharat M., Kalavade, Pranav
Published in IEEE solid-state circuits letters (10.06.2023)
Published in IEEE solid-state circuits letters (10.06.2023)
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Journal Article
30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density
Khakifirooz, Ali, Balasubrahmanyam, Sriram, Fastow, Richard, Gaewsky, Kristopher H., Ha, Chang Wan, Haque, Rezaul, Jungroth, Owen W., Law, Steven, Madraswala, Aliasgar S., Ngo, Binh, Naveen Prabhu, V, Rajwade, Shantanu, Ramamurthi, Karthikeyan, Shenoy, Rohit S., Snyder, Jacqueline, Sun, Cindy, Thimmegowda, Deepak, Pathak, Bharat M., Kalavade, Pranav
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
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Conference Proceeding
DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY DEVICE
CHAO IWEN, PARAT KRISHNA K, GUO XIN, ZHU FENG, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 28.08.2017
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Year of Publication 28.08.2017
Patent
Highly Scalable Vertical Double Gate NOR Flash Memory
Hoon Cho, Kapur, P., Kalavade, P., Saraswat, K.C.
Published in 2007 IEEE International Electron Devices Meeting (01.01.2007)
Published in 2007 IEEE International Electron Devices Meeting (01.01.2007)
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Conference Proceeding
RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING
MIELKE NEAL R, RAJWADE SHANTANU R, PARAT KRISHNA K, KALAVADE PRANAV, RAGHUNATHAN SHYAM SUNDER
Year of Publication 07.10.2015
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Year of Publication 07.10.2015
Patent