A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL
Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yong-Suk Joo, Jae-Hoon Cha, Young-Jung Choi, Moran, P.B., Jin-Hong Ahn
Published in IEEE journal of solid-state circuits (01.11.2007)
Published in IEEE journal of solid-state circuits (01.11.2007)
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Journal Article
Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface
Shin, Dongsuk, Na, Kwang-Jin, Kwon, Daehan, Kang, Jong-Ho, Song, Taeksang, Jung, Ho-Don, Lee, Woo-Young, Park, Ki-Chon, Park, Jung-Hoon, Joo, Yong-Suk, Cha, Jae-Hoon, Jung, Youngho, Kim, Youngran, Han, Donghoon, Choi, Byoung-Jin, Lee, Geun-Il, Cho, Joo-Hwan, Choi, Young-Jung
Published in 2009 Symposium on VLSI Circuits (01.06.2009)
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Published in 2009 Symposium on VLSI Circuits (01.06.2009)
Conference Proceeding
A 1.5-V 3.2Gb/s/pin Graphic DDR4 SDRAM with Dual-Clock System, 4 Phase Input Strobing and Low Jitter Fully Analog DLL
Joo-Hwan Cho, Ki-Won Lee, Byoung-Jin Choi, Geun-Il Lee, Kwang-Jin Na, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yong-Suk Joo, Jae-Hoon Cha, Se-Jun Kim, Young-Jung Choi, Moran, P.B., Jin-Hong Ahn, Joong-Sik Ki
Published in 2006 IEEE Asian Solid-State Circuits Conference (01.11.2006)
Published in 2006 IEEE Asian Solid-State Circuits Conference (01.11.2006)
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Conference Proceeding
A 1.5-V 3.2 Gb/s/pin graphic DDR4 SDRAM with dual-clock system, four-phase input strobing, and low-jitter fully analog DLL : The 2006 asian solid-state circuits conference (A-SSCC'06)
LEE, Ki-Won, CHO, Joo-Hwan, MORAN, Patrick B, AHN, Jin-Hong, CHOI, Byoung-Jin, LEE, Geun-Il, JUNG, Ho-Don, LEE, Woo-Young, PARK, Ki-Chon, JOO, Yong-Suk, CHA, Jae-Hoon, CHOI, Young-Jung
Published in IEEE journal of solid-state circuits (2007)
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Published in IEEE journal of solid-state circuits (2007)
Journal Article