A dual-mode built-in self-test technique for capacitive MEMS devices
Xingguo Xiong, Yu-Liang Wu, Jone, W.-B.
Published in IEEE transactions on instrumentation and measurement (01.10.2005)
Published in IEEE transactions on instrumentation and measurement (01.10.2005)
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Journal Article
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing
Das, S.R., Hossain, A., Biswas, S., Petriu, E.M., Assaf, M.H., Jone, W.-B., Sahinoglu, M.
Published in IEEE transactions on instrumentation and measurement (01.10.2008)
Published in IEEE transactions on instrumentation and measurement (01.10.2008)
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Journal Article
Fault Modeling and Detection for Drowsy SRAM Caches
Wei Pei, Jone, W.-B., Yiming Hu
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.2007)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.2007)
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Journal Article
Crosstalk test pattern generation for dynamic programmable logic arrays
Jianxun Liu, Jone, W.-B., Das, S.R.
Published in IEEE transactions on instrumentation and measurement (01.08.2006)
Published in IEEE transactions on instrumentation and measurement (01.08.2006)
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Journal Article
Fault simulation and response compaction in full scan circuits using HOPE
Das, S.R., Ramamoorthy, C.V., Assaf, M.H., Petriu, E.M., Jone, W.-B., Sahinoglu, M.
Published in IEEE transactions on instrumentation and measurement (01.12.2005)
Published in IEEE transactions on instrumentation and measurement (01.12.2005)
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Journal Article
Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization
Das, S.R., Ramamoorthy, C.V., Assaf, M.H., Petriu, E.M., Jone, W.-B., Sahinoglu, M.
Published in IEEE transactions on instrumentation and measurement (01.10.2005)
Published in IEEE transactions on instrumentation and measurement (01.10.2005)
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Journal Article
A built-in self-testing method for embedded multiport memory arrays
Narayanan, V., Ghosh, S., Jone, W.-B., Das, S.R.
Published in IEEE transactions on instrumentation and measurement (01.10.2005)
Published in IEEE transactions on instrumentation and measurement (01.10.2005)
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Journal Article
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets
Das, S.R., Sudarma, M., Assaf, M.H., Petriu, E.M., Jone, W.-B., Chakrabarty, K., Sahinoglu, M.
Published in IEEE transactions on instrumentation and measurement (01.10.2003)
Published in IEEE transactions on instrumentation and measurement (01.10.2003)
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Journal Article
An efficient BIST method for non-traditional faults of embedded memory arrays
Jone, W.-B., Der-Chen Huang, Das, S.R.
Published in IEEE transactions on instrumentation and measurement (01.10.2003)
Published in IEEE transactions on instrumentation and measurement (01.10.2003)
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Journal Article
Embedded core test generation using broadcast test architecture and netlist scrambling
Jiang, J.H., Jone, W.-B., Shih-Chieh Chang, Ghosh, S.
Published in IEEE transactions on reliability (01.12.2003)
Published in IEEE transactions on reliability (01.12.2003)
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Journal Article
Segmented bus design for low-power systems
Chen, J.Y., Jone, W.B., Wang, J.S., Lu, H.-I., Chen, T.F.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.1999)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.1999)
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Journal Article
An efficient BIST method for distributed small buffers
Jone, W.B., Huang, D.C., Wu, S.C., Lee, K.J.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2002)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2002)
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Journal Article
Testing Analog and Mixed-Signal Circuits With Built-In Hardware-A New Approach
Das, S.R., Zakizadeh, J., Biswas, S., Assaf, M.H., Nayak, A.R., Petriu, E.M., Jone, W.-B., Sahinoglu, M.
Published in IEEE transactions on instrumentation and measurement (01.06.2007)
Published in IEEE transactions on instrumentation and measurement (01.06.2007)
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Journal Article
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays
Arora, V., Jone, W.B., Huang, D.C., Das, S.R.
Published in IEEE transactions on instrumentation and measurement (01.08.2004)
Published in IEEE transactions on instrumentation and measurement (01.08.2004)
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Journal Article
Scan chain fault identification using weight-based codes for SoC circuits
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Conference Proceeding
An efficient parallel transparent diagnostic BIST
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Conference Proceeding
Journal Article