A 32Mb chain FeRAM with segment/stitch array architecture
Shiratake, S., Miyakawa, T., Takeuchi, Y., Ogiwara, R., Kamoshida, M., Hoya, K., Oikawa, K., Ozaki, T., Kunishima, I., Yamakawa, K., Sugimoto, S., Takashima, D., Joachim, H.O., Rehm, N., Wohlfahrt, J., Nagel, N., Beitel, G., Jacob, M., Roehr, T.
Published in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (2003)
Published in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (2003)
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