Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow
Jo, Jihyuck, Kim, Suchang, Park, In-Cheol
Published in IEEE transactions on circuits and systems. I, Regular papers (01.12.2018)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.12.2018)
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Journal Article
DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks
Jo, Jihyuck, Cha, Soyoung, Rho, Dayoung, Park, In-Cheol
Published in IEEE journal of solid-state circuits (01.02.2018)
Published in IEEE journal of solid-state circuits (01.02.2018)
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Journal Article
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory
Lee, Youngjoo, Yoo, Hoyoung, Jung, Jaehwan, Jo, Jihyuck, Park, In-Cheol
Published in IEEE journal of solid-state circuits (01.10.2013)
Published in IEEE journal of solid-state circuits (01.10.2013)
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Journal Article
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
Kong, Byeong Yong, Jo, Jihyuck, Jeong, Hyewon, Hwang, Mina, Cha, Soyoung, Kim, Bongjin, Park, In-Cheol
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2014)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2014)
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Journal Article
DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads
Kim, Seah, Kwon, Hyoukjun, Song, Jinook, Jo, Jihyuck, Chen, Yu-Hsin, Lai, Liangzhen, Chandra, Vikas
Year of Publication 06.12.2022
Year of Publication 06.12.2022
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Journal Article
DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads
Seah, Kim, Kwon, Hyoukjun, Song, Jinook, Jihyuck Jo, Yu-Hsin, Chen, Lai, Liangzhen, Chandra, Vikas
Published in arXiv.org (21.09.2023)
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Published in arXiv.org (21.09.2023)
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