A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
Kim, Wan, Hong, Hyeok-Ki, Roh, Yi-Ju, Kang, Hyun-Wook, Hwang, Sun-Il, Jo, Dong-Shin, Chang, Dong-Jin, Seo, Min-Jae, Ryu, Seung-Tak
Published in IEEE journal of solid-state circuits (01.08.2016)
Published in IEEE journal of solid-state circuits (01.08.2016)
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Journal Article
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation
Kim, Jong-In, Oh, Dong-Ryeol, Jo, Dong-Shin, Sung, Ba-Ro-Saim, Ryu, Seung-Tak
Published in IEEE journal of solid-state circuits (01.10.2015)
Published in IEEE journal of solid-state circuits (01.10.2015)
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Journal Article
Hepatitis C Virus Exploits Death Receptor 6-mediated Signaling Pathway to Facilitate Viral Propagation
Luong, Trang T D, Tran, Giao V Q, Shin, Dong-Jo, Lim, Yun-Sook, Hwang, Soon B
Published in Scientific reports (25.07.2017)
Published in Scientific reports (25.07.2017)
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Journal Article
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8[Formula Omitted] Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration
Oh, Dong-Ryeol, Kim, Jong-In, Dong-Shin, Jo, Woo-Chul, Kim, Dong-Jin, Chang, Seung-Tak Ryu
Published in IEEE journal of solid-state circuits (01.01.2019)
Published in IEEE journal of solid-state circuits (01.01.2019)
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Journal Article
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS
Sung, Ba-Ro-Saim, Jo, Dong-Shin, Jang, Il-Hoon, Lee, Dong-Suk, You, Yong-Sang, Lee, Yong-Hee, Park, Ho-Jin, Ryu, Seung-Tak
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration
Kim, Woo-Cheol, Jo, Dong-shin, Roh, Yi-Ju, Kim, Ye-Dam, Ryu, Seung-Tak
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 \times Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration
Oh, Dong-Ryeol, Kim, Jong-In, Jo, Dong-Shin, Kim, Woo-Chul, Chang, Dong-Jin, Ryu, Seung-Tak
Published in IEEE journal of solid-state circuits (01.01.2019)
Published in IEEE journal of solid-state circuits (01.01.2019)
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Journal Article
A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS
Kyoung-Jun Moon, Hyun-Wook Kang, Dong-Shin Jo, Mi-Young Kim, Seung-Yeob Baek, Choi, Michael, Hyung-Jong Ko, Seung-Tak Ryu
Published in 2017 Symposium on VLSI Circuits (01.06.2017)
Published in 2017 Symposium on VLSI Circuits (01.06.2017)
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Conference Proceeding
A 0.4V 6.5nW 10b 2.5kS/s asynchronous SAR ADC
Dong-Shin Jo, Seung-Tak Ryu
Published in 2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals (01.08.2011)
Published in 2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals (01.08.2011)
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Conference Proceeding
A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique
Hong, Hyeok-Ki, Kang, Hyun-Wook, Jo, Dong-Shin, Lee, Dong-Suk, You, Yong-Sang, Lee, Yong-Hee, Park, Ho-Jin, Ryu, Seung-Tak
Published in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers (01.02.2015)
Published in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers (01.02.2015)
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Conference Proceeding