Physical-aware systematic multiple defect diagnosis
Chen, Po-Juei, Che, Chieh-Chih, Li, James C.-M, Kuo, Shuo-Fen, Hsueh, Pei-Ying, Kuo, Chun-Yi, Lee, Jih-Nung
Published in Chronic diseases and translational medicine (01.09.2014)
Published in Chronic diseases and translational medicine (01.09.2014)
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Journal Article
Methodology of generating dual-cell-aware tests
Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Chao, Mango C.-T
Published in 2017 IEEE 35th VLSI Test Symposium (VTS) (01.04.2017)
Published in 2017 IEEE 35th VLSI Test Symposium (VTS) (01.04.2017)
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Conference Proceeding
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique
Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Hou, Alex Chun-Liang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Chao, Mango C.-T
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
Published in 2016 IEEE 34th VLSI Test Symposium (VTS) (01.04.2016)
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Journal Article
CNN-Based Stochastic Regression for IDDQ Outlier Identification
Yen, Chia-Heng, Chen, Chun-Teng, Wen, Cheng-Yen, Chen, Ying-Yen, Lee, Jih-Nung, Kao, Shu-Yi, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2023)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2023)
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Journal Article
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Nien, Yu-Teng, Wu, Kai-Chiang, Lee, Dong-Zhen, Chen, Ying-Yen, Chen, Po-Lin, Chern, Mason, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2022)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2022)
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Journal Article
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Yang, Cheng-Hao, Yen, Chia-Heng, Wang, Ting-Rui, Chen, Chun-Teng, Chern, Mason, Chen, Ying-Yen, Lee, Jih-Nung, Kao, Shu-Yi, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in 2021 IEEE 39th VLSI Test Symposium (VTS) (25.04.2021)
Published in 2021 IEEE 39th VLSI Test Symposium (VTS) (25.04.2021)
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Conference Proceeding
CNN-based Stochastic Regression for IDDQ Outlier Identification
Chen, Chun-Teng, Yen, Chia-Heng, Wen, Cheng-Yen, Yang, Cheng-Hao, Wu, Kai-Chiang, Chern, Mason, Chen, Ying-Yen, Kuo, Chun-Yi, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Published in 2020 IEEE 38th VLSI Test Symposium (VTS) (01.04.2020)
Published in 2020 IEEE 38th VLSI Test Symposium (VTS) (01.04.2020)
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Conference Proceeding
Layout-Based Dual-Cell-Aware Tests
Wu, Tse-Wei, Lee, Dong-Zhen, Huang, Yu-Hao, Chao, Mango C.-T., Wu, Kai-Chiang, Kao, Shu-Yi, Chen, Ying-Yen, Chen, Po-Lin, Chern, Mason, Lee, Jih-Nung
Published in 2019 IEEE 37th VLSI Test Symposium (VTS) (01.04.2019)
Published in 2019 IEEE 37th VLSI Test Symposium (VTS) (01.04.2019)
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Conference Proceeding
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Nien, Yu-Teng, Wu, Kai-Chiang, Lee, Dong-Zhen, Chen, Ying-Yen, Chen, Po-Lin, Chern, Mason, Lee, Jih-Nung, Kao, Shu-Yi, Chao, Mango Chia-Tso
Published in 2019 IEEE International Test Conference (ITC) (01.11.2019)
Published in 2019 IEEE International Test Conference (ITC) (01.11.2019)
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Conference Proceeding
Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques
Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Chao, Mango C.-T
Published in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2017)
Published in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2017)
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Conference Proceeding
Case study of yield learning through in-house flow of volume diagnosis
Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
Published in 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) (01.04.2013)
Published in 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) (01.04.2013)
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Conference Proceeding
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design
Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu
Published in 2009 International Test Conference (01.11.2009)
Published in 2009 International Test Conference (01.11.2009)
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Conference Proceeding
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Yen, Chia-Heng, Wang, Ting-Rui, Liu, Ching-Min, Yang, Cheng-Hao, Chen, Chun-Teng, Chen, Ying-Yen, Lee, Jih-Nung, Kao, Shu-Yi, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Published in IEEE transactions on semiconductor manufacturing (01.08.2024)
Published in IEEE transactions on semiconductor manufacturing (01.08.2024)
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Journal Article
Case study of process and design performance debugging with Digital Speed Sensor
Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
Published in VLSI Design, Automation and Test(VLSI-DAT) (01.04.2015)
Published in VLSI Design, Automation and Test(VLSI-DAT) (01.04.2015)
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Conference Proceeding
A Model-Based-Random-Forest Framework for Predicting V Mean and Variance Based on Parallel I Measurement
Lin, Chien-Hsueh, Tsai, Chih-Ying, Lee, Kao-Chi, Yu, Sung-Chu, Liau, Wen-Rong, Hou, Alex Chun-Liang, Chen, Ying-Yen, Kuo, Chun-Yi, Lee, Jih-Nung, Chao, Mango C.-T.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2018)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2018)
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Journal Article
Fault pattern oriented defect diagnosis for memories
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Published in International Test Conference, 2003. Proceedings. ITC 2003 (2003)
Published in International Test Conference, 2003. Proceedings. ITC 2003 (2003)
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Conference Proceeding
A Model-Based-Random-Forest Framework for Predicting [Formula Omitted] Mean and Variance Based on Parallel [Formula Omitted] Measurement
Chien-Hsueh, Lin, Chih-Ying Tsai, Kao-Chi, Lee, Sung-Chu, Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen, Chen, Chun-Yi, Kuo, Lee, Jih-Nung, Chao, Mango C-T
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.01.2018)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.01.2018)
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Journal Article
Experiences In Deep Sub-Micron Scan-Based At-Speed Delay Testing
Jih-Nung Lee, Ta-Chia Yeh, Chi-Feng Wu, Shih-Arn Hwang, Chao-Cheng Lee
Published in 2006 International Symposium on VLSI Design, Automation and Test (01.04.2006)
Published in 2006 International Symposium on VLSI Design, Automation and Test (01.04.2006)
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Conference Proceeding
FAME: A Fault-Pattern Based Memory Failure Analysis Framework
Cheng, Kuo-Liang, Wang, Chih-Wea, Lee, Jih-Nung, Chou, Yung-Fa, Huang, Chih-Tsun, Wu, Cheng-Wen
Published in International Conference on Computer Aided Design: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design; 09-13 Nov. 2003 (09.11.2003)
Published in International Conference on Computer Aided Design: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design; 09-13 Nov. 2003 (09.11.2003)
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Conference Proceeding