Low-Leakage SMARTMOS 10W Technology At 0.13μm Node with Optimized Analog, Power and Logic Devices for SOC Design
Hongning Yang, Won-Gi Min, Xin Lin, Newenhouse, V., Huber, J., Hongzhong Xu, Zhihong Zhang, Peterson, B., Jiang-Kai Zuo
Published in 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2008)
Published in 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2008)
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