Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures
Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D.
Published in IEEE transactions on computers (01.03.2009)
Published in IEEE transactions on computers (01.03.2009)
Get full text
Journal Article
Clustered loop buffer organization for low energy VLIW embedded processors
Jayapala, M., Barat, F., Vander Aa, T., Catthoor, F., Corporaal, H., Deconinck, G.
Published in IEEE transactions on computers (01.06.2005)
Published in IEEE transactions on computers (01.06.2005)
Get full text
Journal Article
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures
Lambrechts, A., Raghavan, P., Jayapala, M., Bingfeng Mei, Catthoor, F., Verkest, D.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.01.2009)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.01.2009)
Get full text
Journal Article
Reconfigurable instruction set processors: an implementation platform for interactive multimedia applications
Barat, F., Jayapala, M., de Beeck, P.O., Deconinck, G.
Published in Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256) (2001)
Published in Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256) (2001)
Get full text
Conference Proceeding
Power breakdown analysis for a heterogeneous NoC platform running a video application
Lambrechts, A., Raghavan, P., Leroy, A., Talavera, G., Aa, T.V., Jayapala, M., Catthoor, F., Verkest, D., Deconinck, G., Corporaal, H., Robert, F., Carrabina, J.
Published in 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)
Published in 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)
Get full text
Conference Proceeding
Instruction buffering exploration for low energy VLIWs with instruction clusters
Vander An, T., Jayapala, M., Barat, F., Deconinck, G., Lauwereins, R., Catthoor, F., Corporaal, H.
Published in ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) (2004)
Published in ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) (2004)
Get full text
Conference Proceeding
EMPIRE: Empirical power/area/timing models for register files
Raghavan, Praveen, Lambrechts, Andy, Jayapala, Murali, Catthoor, Francky, Verkest, Diederik
Published in Microprocessors and microsystems (01.06.2009)
Published in Microprocessors and microsystems (01.06.2009)
Get full text
Journal Article
Design style case study for embedded multi media compute nodes
Lambrechts, A., Aa, T.V., Jayapala, M., Talavera, G., Leroy, A., Shickova, A., Barat, F., Bingfeng Mei, Catthoor, F., Verkest, D., Deconinck, G., Corporaal, H., Robert, F., Bordoll, J.C.
Published in 25th IEEE International Real-Time Systems Symposium (2004)
Published in 25th IEEE International Real-Time Systems Symposium (2004)
Get full text
Conference Proceeding
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy
van der Perre, L., Bougard, B., Craninckx, J., Dehaene, W., Hollevoet, L., Jayapala, M., Marchal, P., Miranda, M., Raghavan, P., Schuster, T., Wambacq, P., Catthoor, F., Vanbekbergen, P.
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Get full text
Conference Proceeding
Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors
Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D., Corporaal, H.
Published in 2007 Design, Automation & Test in Europe Conference & Exhibition (01.04.2007)
Published in 2007 Design, Automation & Test in Europe Conference & Exhibition (01.04.2007)
Get full text
Conference Proceeding
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor
Lambrechts, A., Raghavan, P., Jayapala, M., Catthoor, F., Verkest, D.
Published in 21st International Conference on VLSI Design (VLSID 2008) (01.01.2008)
Published in 21st International Conference on VLSI Design (VLSID 2008) (01.01.2008)
Get full text
Conference Proceeding
Automated architecture exploration for low energy reconfigurable AGU
Taniguchi, I., Jayapala, M., Raghavan, P., Catthoor, F., Sakanushi, K., Takeuchi, Y., Imai, M.
Published in 2011 International SoC Design Conference (01.11.2011)
Published in 2011 International SoC Design Conference (01.11.2011)
Get full text
Conference Proceeding
Compilation Technique for Loop Overhead Minimization
Kroupis, N., Raghavan, P., Jayapala, M., Catthoor, F., Soudris, D.
Published in 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (01.08.2009)
Published in 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (01.08.2009)
Get full text
Conference Proceeding
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors
Taniguchi, I., Jayapala, M., Raghavan, P., Catthoor, F., Sakanushi, K., Takeuchi, Y., Imai, M.
Published in 2009 Asia and South Pacific Design Automation Conference (01.01.2009)
Published in 2009 Asia and South Pacific Design Automation Conference (01.01.2009)
Get full text
Conference Proceeding
Operation shuffling over cycle boundaries for low energy L0 clustering
Kobayashi, Y., Jayapala, M., Raghavan, P., Catthoor, F., Imai, M.
Published in 2008 International Conference on Application-Specific Systems, Architectures and Processors (01.07.2008)
Published in 2008 International Conference on Application-Specific Systems, Architectures and Processors (01.07.2008)
Get full text
Conference Proceeding
Software pipelining for coarse-grained reconfigurable instruction set processors
Barat, F., Jayapala, M., Op de Beeck, P., Deconinck, G.
Published in Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design (2002)
Published in Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design (2002)
Get full text
Conference Proceeding
Locality optimization in wireless applications
Absar, Javed, Li, Min, Raghavan, Praveen, Lambrechts, Andy, Jayapala, Murali, Vandecappelle, Arnout, Catthoor, Francky
Published in 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (30.09.2007)
Published in 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (30.09.2007)
Get full text
Conference Proceeding
Instruction Transfer And Storage Exploration for Low Energy VLIWs
Vander Aa, T., Jayapala, M., Corporaal, H., Catthoor, F., Deconinck, G.
Published in 2006 IEEE Workshop on Signal Processing Systems Design and Implementation (01.10.2006)
Published in 2006 IEEE Workshop on Signal Processing Systems Design and Implementation (01.10.2006)
Get full text
Conference Proceeding