Search Results - "Javidan, Javad" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices

Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices

by Nabipour, Saeideh, Javidan, Javad, Drechsler, Rolf
Published in Memories - Materials, Devices, Circuits and Systems (01.04.2024)

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Journal Article

High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology

High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology

by Javidan, Javad, Atarodi, Mojtaba, Luong, Howard C
Published in IEEE transactions on circuits and systems. II, Express briefs (01.11.2010)

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Journal Article

A Novel Fuzzy RPID Controller for Multiarea AGC with IABC Optimization

A Novel Fuzzy RPID Controller for Multiarea AGC with IABC Optimization

by Javidan, Javad, Ghasemi, Ali
Published in Journal of engineering (Cairo, Egypt) (01.01.2013)

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Journal Article

Design of a ZVS PWM DC-DC converter for high gain applications

Design of a ZVS PWM DC-DC converter for high gain applications

by Javidan, Javad
Published in International journal of circuit theory and applications (01.05.2016)

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Journal Article

Polarization-independent tunable multi-band terahertz absorber based on graphene structure to design the ultra-high sensitive biosensors

Polarization-independent tunable multi-band terahertz absorber based on graphene structure to design the ultra-high sensitive biosensors

by Rafighirani, Yousef, Javidan, Javad, Heidarzadeh, Hamid
Published in Physica scripta (01.07.2024)

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Journal Article

Development of a Multi-Band High-Sensitivity Polarization-Independent Absorber: A Biosensor for Simultaneous Detection of Multiple Cancer Biomarkers

Development of a Multi-Band High-Sensitivity Polarization-Independent Absorber: A Biosensor for Simultaneous Detection of Multiple Cancer Biomarkers

by Rafighirani, Yousef, Javidan, Javad, Heidarzadeh, Hamid
Published in Plasmonics (Norwell, Mass.) (02.08.2024)

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Journal Article

A bidirectional high step‐up multi‐input DC‐DC converter with soft switching

A bidirectional high step‐up multi‐input DC‐DC converter with soft switching

by KhademiAstaneh, Parastou, Javidan, Javad, Valipour, Khalil, Akbarimajd, Adel
Published in International transactions on electrical energy systems (01.01.2019)

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Journal Article

A bidirectional high step-up multi-input DC-DC converter with soft switching: Multi Input DC-DC Converter

A bidirectional high step-up multi-input DC-DC converter with soft switching: Multi Input DC-DC Converter

by KhademiAstaneh, Parastou, Javidan, Javad, Valipour, Khalil, Akbarimajd, Adel
Published in International transactions on electrical energy systems (01.01.2019)

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Journal Article

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

by Nabipour, Saeideh, Javidan, Javad
Year of Publication 16.07.2023

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Journal Article

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

by Nabipour, Saeideh, Javidan, Javad
Year of Publication 23.06.2023

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Journal Article

Implementation of a fully integrated 30-dBm RF CMOS linear power amplifier with power combiner

Implementation of a fully integrated 30-dBm RF CMOS linear power amplifier with power combiner

by Javidan, Javad, Atarodi, S. Mojtaba
Published in International journal of electronics and communications (01.06.2011)

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Journal Article

Error Detection Mechanism Based On Bch Decoder And Root Finding Of Polynomial Over Finite Fields

Error Detection Mechanism Based On Bch Decoder And Root Finding Of Polynomial Over Finite Fields

by Nabipour, Saeideh, Javidan, Javad, Fatin, Gholamreza Zare
Published in Journal of Mathematics and Computer Science (31.10.2014)

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Journal Article

Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 − µm CMOS technology

Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 − µm CMOS technology

by Javidan, Javad, Atarodi, S. Mojtaba, Luong, Howard C.
Published in International journal of circuit theory and applications (01.09.2012)

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Journal Article

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

by Nabipour, Saeideh, Javidan, Javad, Fatin, Gholamreza Zare
Year of Publication 27.09.2022

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Journal Article

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

by Nabipour, Saeideh, Javidan, Javad
Published in arXiv.org (26.07.2023)

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Paper

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

by Nabipour, Saeideh, Javidan, Javad
Published in arXiv.org (16.07.2023)

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Paper

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

by Nabipour, Saeideh, Fatin, Gholamreza Zare, Javidan, Javad
Year of Publication 16.07.2020

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Journal Article

An Efficient Digital Watermarking Algorithm Based on DCT and BCH Error Correcting Code

An Efficient Digital Watermarking Algorithm Based on DCT and BCH Error Correcting Code

by Nabipour, Saeideh, Javidan, Javad, Khorrami, Majid, Azimzadeh, Jila
Year of Publication 03.08.2021

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Journal Article

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

by Nabipour, Saeideh, Gholamreza Zare Fatin, Javidan, Javad
Published in arXiv.org (13.09.2023)

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Paper

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

by Nabipour, Saeideh, Javidan, Javad, Gholamreza Zare Fatin
Published in arXiv.org (14.03.2023)

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Paper