Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15
Wolpert, David, Berry, Christopher, Bell, Brian, Jatkowski, Adam, Surprise, Jesse, Isakson, John, Geva, Ofer, Deskin, Brian, Cichanowski, Mark, Hamid, Dina, Cavitt, Chris, Fredeman, Gregory, Kannambadi, Dinesh, Saporito, Anthony, Mishra, Ashutosh, Buyuktosunoglu, Alper, Webel, Tobias, Lobo, Preetham, Bertran, Ramon, Parashurama, Pradeep Bhadravati, Chidambarrao, Dureseti, Bruen, Brandon, Wagstaff, Alan, Lukes, Eric, Carey, Sean, Shi, Hunter, Romain, Michael, Logsdon, Paul, Agarwal, Ishita
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
IBM Telum: a 16-Core 5+ GHz DCM
Geva, Ofer, Berry, Chris, Sonnelitter, Robert, Wolpert, David, Collura, Adam, Strach, Thomas, Phan, Di, Lichtenau, Cedric, Buyuktosunoglu, Alper, Harrer, Hubert, Zitz, Jeffrey, Marquart, Chad, Malone, Douglas, Webel, Tobias, Jatkowski, Adam, Isakson, John, Hamid, Dina, Cichanowski, Mark, Romain, Michael, Hasan, Faisal, Williams, Kevin, Surprise, Jesse, Cavitt, Chris, Cohen, Mark
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
Warnock, James, Yuen Chan, Harrer, Hubert, Carey, Sean, Salem, Gerard, Malone, Doug, Puri, Ruchir, Zitz, Jeffrey A., Jatkowski, Adam, Strevig, Gerald, Datta, Ayan, Gattiker, Anne, Bansal, Aditya, Mayer, Guenter, Yiu-Hing Chan, Mayo, Mark, Rude, David L., Sigal, Leon, Strach, Thomas, Smith, Howard H., Huajun Wen, Pak-kin Mak, Shum, C-L Kevin, Plass, Donald, Webb, Charles
Published in IEEE journal of solid-state circuits (01.01.2014)
Published in IEEE journal of solid-state circuits (01.01.2014)
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Journal Article
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor
Berry, Christopher, Bell, Brian, Jatkowski, Adam, Surprise, Jesse, Isakson, John, Geva, Ofer, Deskin, Brian, Cichanowski, Mark, Hamid, Dina, Cavitt, Chris, Fredeman, Gregory, Saporito, Anthony, Mishra, Ashutosh, Buyuktosunoglu, Alper, Webel, Tobias, Lobo, Preetham, Parashurama, Pradeep, Bertran, Ramon, Chidambarrao, Dureseti, Wolpert, David, Bruen, Brandon
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding
5.5GHz system z microprocessor and multi-chip module
Warnock, J., Chan, Y. H., Harrer, H., Rude, D., Puri, R., Carey, S., Salem, G., Mayer, G., Yiu-Hing Chan, Mayo, M., Jatkowski, A., Strevig, G., Sigal, L., Datta, A., Gattiker, A., Bansal, A., Malone, D., Strach, T., Huajun Wen, Pak-Kin Mak, Chung-Lung Shum, Plass, D., Webb, C.
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding
Constraint-driven pin optimization for hierarchical design convergence
Saha Sourav, Palumbo Joseph J, Berry Christopher J, St. Juste Eddy, Jatkowski Adam R, Schell Timothy A, Ramji Shyam, Darden Randall J
Year of Publication 02.01.2018
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Year of Publication 02.01.2018
Patent
CONSTRAINT-DRIVEN PIN OPTIMIZATION FOR HIERARCHICAL DESIGN CONVERGENCE
Saha Sourav, Palumbo Joseph J, Berry Christopher J, St. Juste Eddy, Jatkowski Adam R, Schell Timothy A, Ramji Shyam, Darden Randall J
Year of Publication 11.05.2017
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Year of Publication 11.05.2017
Patent
Automated method for buffering in a VLSI design
PALUMBO JOSEPH J, MALGIOGLIO FRANK, JATKOWSKI ADAM R, LASSETER BRIAN A
Year of Publication 30.08.2011
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Year of Publication 30.08.2011
Patent
Automated method for buffering in a VLSI design
Malgioglio, Frank, Jatkowski, Adam R, Lasseter, Brian A, Palumbo, Joseph J
Year of Publication 30.08.2011
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Year of Publication 30.08.2011
Patent
Automated Method for Buffering in a VLSI Design
PALUMBO JOSEPH J, MALGIOGLIO FRANK, JATKOWSKI ADAM R, LASSETER BRIAN A
Year of Publication 20.08.2009
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Year of Publication 20.08.2009
Patent