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"Janmye Sung"
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"Janmye Sung"
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High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI
by
Lu, C.-Y.
,
Sung, J.J.
,
Kirsch, H.C.
,
Tsai, N.-S.
,
Liu, R.
,
Manocha, A.S.
,
Hillenius, S.J.
Published in
IEEE transactions on electron devices
(01.11.1989)
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A new analytical model and the impact of base charge storage on base potential distribution, emitter current crowding and base resistance
by
Tzu-Yin Chiu
,
Tien
,
Janmye Sung
,
Liu
Published in
1992 International Technical Digest on Electron Devices Meeting
(1992)
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Submicrometer salicide CMOS devices with self-aligned shallow/deep junctions
by
Lu, C.-Y.
,
Sung, J.J.
,
Yu, C.-H.D.
Published in
IEEE electron device letters
(01.11.1989)
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SEMICONDUCTOR INTEGRATED CIRCUIT
by
JANMYE
,
SUNG
,
KUO-HUA, LEE
,
WILLIAM JOHN, NAGY
Year of Publication
01.06.2000
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Patent
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FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
by
JHON NAGY WILLIAM
,
KUO-HUA, LEE
,
THOMAS EVANS ADAMS
,
JANMYE SUNG
Year of Publication
15.04.2000
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Manufacture method of high-density flat-unit type mask ROM
by
SUNG
,
JANMYE
Year of Publication
21.11.2002
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Method fabricating a DRAM cell with an area equal to four times the used minimum feature
by
SUNG JANMYE
Year of Publication
06.03.2001
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Patent
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Capacitor over bit line structure using a straight bit line shape
by
SUNG
;
JANMYE
Year of Publication
24.10.2000
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Capacitor over bit line structure using a straight bit line shape
by
SUNG
;
JANMYE
Year of Publication
15.02.2000
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Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance
by
SUNG
;
JANMYE
Year of Publication
28.12.1999
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Method for fabrication of a one gigabit capacitor over bit line DRAM cell with an area equal to eight times the used minimum feature
by
SUNG
;
JANMYE
Year of Publication
09.03.1999
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Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip
by
SUNG
;
JANMYE
Year of Publication
12.01.1999
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Reduced mask DRAM process
by
SUNG
;
JANMYE
Year of Publication
15.09.1998
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Dram cell capacitor fabrication method
by
SUNG
;
JANMYE
Year of Publication
04.08.1998
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Memory cell array with a self-aligned, buried bit line
by
SUNG
;
JANMYE
Year of Publication
19.05.1998
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Low cycle time CMOS process
by
SUNG
;
JANMYE
Year of Publication
17.03.1998
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Low cycle time CMOS process
by
SUNG
;
JANMYE
Year of Publication
12.11.1996
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Reduced mask DRAM process
by
SUNG
;
JANMYE
Year of Publication
27.08.1996
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method for fabricating an embedded vertical bipolar transistor and a memory cell
by
SUNG
;
JANMYE
Year of Publication
20.08.1996
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Static RAM memory integrated circuit with balanced resistance
by
LEE, KUO-HUA
,
SUNG
,
JANMYE
Year of Publication
10.04.2002
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