Power management of the third generation intel core micro architecture formerly codenamed ivy bridge
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Published in 2012 IEEE Hot Chips 24 Symposium (HCS) (01.08.2012)
Published in 2012 IEEE Hot Chips 24 Symposium (HCS) (01.08.2012)
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Conference Proceeding
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Year of Publication 08.02.2024
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Year of Publication 08.02.2024
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A 22nm IA multi-CPU and GPU System-on-Chip
Damaraju, S., George, V., Jahagirdar, S., Khondker, T., Milstrey, R., Sarkar, S., Siers, S., Stolero, I., Subbiah, A.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS
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Year of Publication 25.05.2021
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Year of Publication 25.05.2021
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SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS
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Year of Publication 25.05.2021
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Year of Publication 25.05.2021
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Penryn: 45-nm next generation Intel® core™ 2 processor
Varghese George, Sanjeev Jahagirdar, Chao Tong, Smits, Ken, Satish Damaraju, Siers, Scott, Ves Naydenov, Tanveer Khondker, Sanjib Sarkar, Puneet Singh
Published in 2007 IEEE Asian Solid-State Circuits Conference (01.11.2007)
Published in 2007 IEEE Asian Solid-State Circuits Conference (01.11.2007)
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Conference Proceeding
PLATFORM AGNOSTIC POWER MANAGEMENT
MORAN DOUGLAS R, VAZ IRWIN J, BIBIKAR VASUDEV, KLINGLESMITH MICHAEL T, GEORGE VARGHESE, KNOLLA WILLIAM, SINGH HARTEJ, ZAHIR ACHMED R, JAHAGIRDAR SANJEEV S
Year of Publication 23.09.2014
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Year of Publication 23.09.2014
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Dynamic power budget allocation in multi-processor system
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 16.01.2024
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Year of Publication 16.01.2024
Patent
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 02.02.2023
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Year of Publication 02.02.2023
Patent
Dynamic power budget allocation in multi-processor system
Borole, Bhushan, Jahagirdar, Sanjeev, Sinha, Kamal, Kaburlasos, Nikos, Rajwani, Iqbal
Year of Publication 08.11.2022
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Year of Publication 08.11.2022
Patent
METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW
NARVAEZ PAOLO, HAHN SCOTT D, RAPPOPORT RINAT, BRANDT JASON W, CHOUBAL ASHISH V, HENROID ANDREW D, HERDRICH ANDREW J, MISHAELI MICHAEL, GORBATOV EUGENE, NAIK MISHALI, KHANNA GAURAV, SHAFI HISHAM, PRABHAKARAN ABIRAMI, SRINIVASA GANAPATI N, WEISSMANN ELIERZER, BRETT PAUL, SODHI INDER M, LENZ ORON, JAHAGIRDAR SANJEEV S, FISCHER STEPHEN A, FENGER RUSSEL J, KOUFATY DAVID A, NAVEH ALON, SUBBAREDDY DHEERAJ R, TOLL BRET L
Year of Publication 24.09.2014
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Year of Publication 24.09.2014
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POWER SAVINGS FOR NEURAL NETWORK ARCHITECTURE WITH ZERO ACTIVATIONS DURING INFERENCE
JAHAGIRDAR, Sanjeev, SURTI, Prasoonkumar, DESAI, Kinchit, RAY, Joydeep
Year of Publication 04.08.2021
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Year of Publication 04.08.2021
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Adaptive multibit bus for energy optimization
Ganpule, Tapan A, Jahagirdar, Sanjeev S, Thaploo, Anupama A, Koker, Altug, Ray, Joydeep, Appu, Abhishek R
Year of Publication 25.04.2023
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Year of Publication 25.04.2023
Patent
Disaggregation of system-on-chip (SOC) architecture
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 08.10.2024
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Year of Publication 08.10.2024
Patent
OPDELING AF SOC-ARKITEKTUR
Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Year of Publication 23.09.2024
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Year of Publication 23.09.2024
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