A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
Bedeschi, F., Fackenthal, R., Resta, C., Donze, E.M., Jagasivamani, M., Buda, E.C., Pellizzer, F., Chow, D.W., Cabrini, A., Calvi, G., Faravelli, R., Fantini, A., Torelli, G., Mills, D., Gastaldi, R., Casagrande, G.
Published in IEEE journal of solid-state circuits (01.01.2009)
Published in IEEE journal of solid-state circuits (01.01.2009)
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Journal Article
Conference Proceeding
Split-fabrication obfuscation: Metrics and techniques
Jagasivamani, Meenatchi, Gadfort, Peter, Sika, Michel, Bajura, Michael, Fritze, Michael
Published in 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (01.05.2014)
Published in 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (01.05.2014)
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Conference Proceeding
Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die
Jagasivamani, Meenatchi, Walden, Candace, Singh, Devesh, Kang, Luyi, Li, Shang, Asnaashari, Mehdi, Dubois, Sylvain, Jacob, Bruce, Yeung, Donald
Published in IEEE MICRO (01.11.2019)
Published in IEEE MICRO (01.11.2019)
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Journal Article
A Multi-Level-Cell Bipolar-Selected Phase-Change Memory
Bedeschi, Ferdinando, Fackenthal, Rich, Resta, Claudio, Donze, Enzo Michele, Jagasivamani, Meenatchi, Buda, Egidio, Pellizzer, Fabio, Chow, David, Cabrini, Alessandro, Calvi, Giacomo Matteo Angelo, Faravelli, Roberto, Fantini, Andrea, Torelli, Guido, Mills, Duane, Gastaldi, Roberto, Casagrande, Giulio
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
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Conference Proceeding
Model And Evaluation Of A Superconducting-Logic Based Hybrid CPU-Accelerator System
Jagasivamani, Meenatchi, Fong, Christine, Goodnow, Kenneth, Voigt, Robert
Published in 2022 Annual Modeling and Simulation Conference (ANNSIM) (18.07.2022)
Published in 2022 Annual Modeling and Simulation Conference (ANNSIM) (18.07.2022)
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Conference Proceeding
Tileable Monolithic ReRAM Memory Design
Jagasivamani, Meenatchi, Walden, Candace, Singh, Devesh, Kang, Luyi, Asnaashari, Mehdi, Dubois, Sylvain, Jacob, Bruce, Yeung, Donald
Published in 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) (01.04.2020)
Published in 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) (01.04.2020)
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Conference Proceeding
Interleaved array architecture
FACKENTHAL RICHARD E, BEDESCHI FERDINANDO, JAGASIVAMANI MEENATCHI, DONZE ENZO M
Year of Publication 13.01.2015
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Year of Publication 13.01.2015
Patent
Method of accelerating phase change memory writes
DONZE', ENZO, RAVI, GUTALA, KO, ANTHONY, BEDESCHI, FERDINANDO, FACKENTHAL, RICH E, JAGASIVAMANI, MEENATCHI
Year of Publication 23.07.2014
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Year of Publication 23.07.2014
Patent
Programming bit alterable memories
FACKENTHAL RICHARD, BEDESCHI FERDINANDO, JAGASIVAMANI MEENATCHI, DONZE ENZO
Year of Publication 22.11.2011
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Year of Publication 22.11.2011
Patent
Programming bit alterable memories
Jagasivamani, Meenatchi, Fackenthal, Richard, Bedeschi, Ferdinando, Donze, Enzo
Year of Publication 22.11.2011
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Year of Publication 22.11.2011
Patent
Adaptive wordline programming bias of a phase change memory
FACKENTHAL RICHARD E, BEDESCHI FERDINANDO, JAGASIVAMANI MEENATCHI, ANNAVAJJHALA RAVI, DONZE ENZO M
Year of Publication 29.10.2013
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Year of Publication 29.10.2013
Patent