Integration and Electrical Properties of Carbon Nanotube Array for Interconnect Applications
Young-Moon Choi, Sunwoo Lee, Hong Sik Yoon, Moon-Sook Lee, Hajin Kim, Intaek Han, Yoonho Son, In-Seok Yeo, Chung, U.-I., Joo-Tae Moon
Published in 2006 Sixth IEEE Conference on Nanotechnology (2006)
Published in 2006 Sixth IEEE Conference on Nanotechnology (2006)
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Conference Proceeding
Semiconductor Memory Devices Including Offset Bit Lines
MOON JOO-TAE, CHO HAN-KU, YEO GI-SUNG, BAEK KYOUNG-YUN, GOO DOO-HOON, WOO SANG-GYUN
Year of Publication 03.09.2009
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Year of Publication 03.09.2009
Patent
Semiconductor Memory Devices Including Extended Memory Elements
MOON JOO-TAE, CHO HAN-KU, GOO DON-HOON, YEO GI-SUNG, BAEK KYOUNG-YUN, WOO SANG-GYUN
Year of Publication 03.09.2009
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Year of Publication 03.09.2009
Patent
Semiconductor memory devices including offset active regions
MOON JOO-TAE, CHO HAN-KU, YEO GI-SUNG, BAEK KYOUNG-YUN, GOO DOO-HOON, WOO SANG-GYUN
Year of Publication 16.06.2009
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Year of Publication 16.06.2009
Patent
A new ALD-TiN/CoSi/sub 2/ contact plug process for reliable and low defect density bit-line integration in sub-quarter micron giga-bit DRAM
Seong Geon Park, Sang-Bom Kang, Gil Heyun Choi, U In Chung, Joo Tae Moon
Published in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519) (2002)
Published in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519) (2002)
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Conference Proceeding
Resist composition and method of forming fine pattern using the same
MOON, JOO-TAE, CHOI, SANG-JUN, KANG, YOOL, CHUNG, JEONG-HEE, WOO, SANG-GYUN
Year of Publication 21.09.2005
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Year of Publication 21.09.2005
Patent
Semiconductor memory devices including offset active regions
MOON, JOO-TAE, GOO, DOO-HOON, CHO, HAN-KU, WOO, SANG-GYUN, YEO, GI-SUNG
Year of Publication 01.05.2007
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Year of Publication 01.05.2007
Patent
The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device
Jin-Hwa Heo, Soo-Jin Hong, Guk-Hyon Yon, Yu-Gyun Shin, Fujihara, K., U-In Chung, Joo-Tae Moon
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)
Published in 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) (2003)
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Conference Proceeding
Verfahren zur Erzeugung einer feinen Struktur in einem Halbleitersubstrat und Resistzusammensetzung hierfür
MOON, JOO-TAE, CHOI, SANG-JUN, KANG, YOOL, CHUNG, JEONG-HEE, WOO, SANG-GYUN
Year of Publication 27.12.2012
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Year of Publication 27.12.2012
Patent
Resist compositions including thermal crosslinking agents
MOON JOO-TAE, CHOI SANG-JUN, KANG YOOL, CHUNG JEONG-HEE, WOO SANG-GYUN
Year of Publication 03.02.2005
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Year of Publication 03.02.2005
Patent
Methods for forming line patterns in semiconductor substrates
MOON JOO-TAE, CHOI SANG-JUN, KANG YOOL, CHUNG JEONG-HEE, WOO SANG-GYUN
Year of Publication 12.10.2004
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Year of Publication 12.10.2004
Patent
Methods for forming line patterns in semiconductor substrates
Choi, Sang-jun, Kang, Yool, Moon, Joo-tae, Chung, Jeong-hee, Woo, Sang-gyun
Year of Publication 12.10.2004
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Year of Publication 12.10.2004
Patent
Electrical analysis on the drain current of the ultra shallow junction by laser annealing
Soo Jin Hong, Young Pil Kim, Jin Hwa Heo, Gook-Hyun Yon, Gung Ho Buh, Yu Gyun Shin, Uin Chung, Joo Tae Moon
Published in Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) (2004)
Published in Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) (2004)
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Conference Proceeding