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"JIANG JYH-MIN"
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"JIANG JYH-MIN"
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High voltage ESD protection device with very low snapback voltage
by
JIANG JYH
-
MIN
,
LIU RUEY-HSIN
,
LEE JIAN-HSING
,
LIU KUOIO
Year of Publication
08.07.2003
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High voltage ESD protection device with very low snapback voltage
by
Jiang
,
Jyh
-
Min
,
Liu, Kuo-Chio
,
Lee, Jian-Hsing
,
Liu, Ruey-Hsin
Year of Publication
08.07.2003
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Novel high voltage ESD protection device with very low snapback voltage
by
Jiang
,
Jyh
-
Min
,
Liu, Kuo-Chio
,
Lee, Jian-Hsing
,
Liu, Ruey-Hsin
Year of Publication
22.08.2002
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Novel high voltage ESD protection device with very low snapback voltage
by
JIANG JYH
-
MIN
,
LIU RUEY-HSIN
,
LEE JIAN-HSING
,
LIU KUOIO
Year of Publication
22.08.2002
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High voltage transistor using P+ buried layer
by
Tsai, Jun-Lin
,
Liu, Ruey-Hsin
,
Jiang
,
Jyh
-
Min
,
Hwang, Jei-Feng
Year of Publication
28.05.2002
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High voltage transistor using P+ buried layer
by
JIANG JYH
-
MIN
,
TSAI JUN-LIN
,
LIU RUEY-HSIN
,
HWANG JEI-FENG
Year of Publication
28.05.2002
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A novel high voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain
by
JIANG JYH
-
MIN
,
LIU RUEY-HSIN
,
LEE JIAN-HSING
,
LIU KUOIO
Year of Publication
27.11.2001
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Method of fabricating a high voltage transistor using P+ buried layer
by
TSAZ JUN-LIN
,
JIANG JYH
-
MIN
,
LIU RUEY-HSIN
,
HWANG JEI-FENG
Year of Publication
18.09.2001
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Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same
by
JIANG JYH
-
MIN
,
LIOU RUEY-HSIN
,
WU CHEN-BAU
,
LIU KOUIO
Year of Publication
24.07.2001
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Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage
by
JIANG JYH
-
MIN
,
LIOU RUEY-HSIN
,
TSAI JUN-LIN
,
HWANG JEI-FENG
Year of Publication
05.06.2001
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