A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory
Dong-Il Moon, Jee-Yeon Kim, Hyunjae Jang, Hee-Jeong Hong, Choong Ki Kim, Jae-Sub Oh, Min-Ho Kang, Jeoung-Woo Kim, Yang-Kyu Choi
Published in IEEE electron device letters (01.12.2014)
Published in IEEE electron device letters (01.12.2014)
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Journal Article
Low-temperature high-performance In-Ga-Sn-O thin-film transistors with Al2O3 grown by a facile dual-atomic layer deposition
Jang, Hyunjae, Oh, Changyong, Kim, Tae Hyun, Kim, Hyeong Wook, Lee, Sang Ik, Kim, Bo Sung
Published in Journal of alloys and compounds (15.09.2021)
Published in Journal of alloys and compounds (15.09.2021)
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Journal Article
Influence of oxygen-related defects on In-Ga-Sn-O semiconductor due to plasma-enhanced atomic layer deposition of Al2O3 for low-temperature thin-film transistor in terms of electrical properties
Kim, Hyeong Wook, Oh, Changyong, Jang, Hyunjae, Kim, Min Young, Kim, Bo Sung
Published in Journal of alloys and compounds (15.10.2022)
Published in Journal of alloys and compounds (15.10.2022)
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Journal Article
Bridging TCAD and AI: Its Application to Semiconductor Design
Jeong, Changwook, Myung, Sanghoon, Huh, In, Choi, Byungseon, Kim, Jinwoo, Jang, Hyunjae, Lee, Hojoon, Park, Daeyoung, Lee, Kyuhun, Jang, Wonik, Ryu, Jisu, Cha, Moon-Hyun, Choe, Jae Myung, Shim, Munbo, Kim, Dae Sin
Published in IEEE transactions on electron devices (01.11.2021)
Published in IEEE transactions on electron devices (01.11.2021)
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Journal Article
SIMULATION SYSTEM FOR SEMICONDUCTOR PROCESS AND SIMULATION METHOD THEREOF
HUH IN, JEONG CHANGWOOK, NOH HYEON KYUN, JANG HYUNJAE, MYUNG SANGHOON, PARK MIN CHUL
Year of Publication 03.06.2021
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Year of Publication 03.06.2021
Patent
A mechanical and electrical transistor structure (METS) with a sub-2 nm nanogap for effective voltage scaling
Lee, Byung-Hyun, Moon, Dong-Il, Jang, HyunJae, Kim, Chang-Hoon, Seol, Myeong-Lok, Choi, Ji-Min, Lee, Dong-Il, Kim, Min-Wu, Yoon, Jun-Bo, Choi, Yang-Kyu
Published in Nanoscale (21.07.2014)
Published in Nanoscale (21.07.2014)
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Journal Article
A mechanical and electrical transistor structure (METS) with a sub-2 nm nanogap for effective voltage scalingElectronic supplementary information (ESI) available: The setup process for the formation of an ultra-narrow air gap and the XPS results of analysing the component of each dielectric are provided. In order to support the experimental and the FEM simulation results, revamped analytical modeling for the METS to extract VP is given. Widened margins of the critical dimensions, in this case th
Lee, Byung-Hyun, Moon, Dong-Il, Jang, HyunJae, Kim, Chang-Hoon, Seol, Myeong-Lok, Choi, Ji-Min, Lee, Dong-Il, Kim, Min-Wu, Yoon, Jun-Bo, Choi, Yang-Kyu
Year of Publication 26.06.2014
Year of Publication 26.06.2014
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Journal Article
SEMICONDUCTOR FUALT ANALYSIS DEVICE AND METHOD FOR ANALYZING FAULT THEREOF
KIM HYUNGTAE, JEON MIN CHUL, JEONG CHANGWOOK, KO JEONGHOON, RYU JISU, JANG HYUNJAE, MYUNG SANGHOON, PARK MIN CHUL, LI YUNRONG
Year of Publication 27.12.2019
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Year of Publication 27.12.2019
Patent
METHOD AND APPARATUS FOR INFERRING SEMICONDUCTOR MEASUREMENT RESULTS BASED ON ARTIFICIAL INTELLIGENCE
Kim, Yeji, Park, Minchul, Jang, Hyunjae, Kim, Seongryeol, Huh, In, Kim, Satbyul, Kim, Younggu
Year of Publication 27.06.2024
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Year of Publication 27.06.2024
Patent
A Novel Approach for Semiconductor Etching Process with Inductive Biases
Myung, Sanghoon, Jang, Hyunjae, Choi, Byungseon, Ryu, Jisu, Kim, Hyuk, Park, Sang Wuk, Jeong, Changwook, Kim, Dae Sin
Year of Publication 06.04.2021
Year of Publication 06.04.2021
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Journal Article
Simulation system for semiconductor process and simulation method thereof
Park, Min-Chul, Jang, Hyunjae, Jeong, Changwook, Noh, Hyeon Kyun, Huh, In, Myung, Sanghoon
Year of Publication 30.01.2024
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Year of Publication 30.01.2024
Patent
MODELING METHOD OF NEURAL NETWORK FOR SIMULATION IN SEMICONDUCTOR DESIGN PROCESS, SIMULATION METHOD IN SEMICONDUCTOR DESIGN PROCESS USING THE SAME, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCTOR DESIGN SYSTEM PERFORMING THE SAME
Moon, Hyowon, Jang, Hyunjae, Choe, Jaemyung, Huh, In, Kang, Bogyeong, Nam, Yunjun, Choi, Byungseon
Year of Publication 25.01.2024
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Year of Publication 25.01.2024
Patent
MODELING METHOD OF NEURAL NETWORK FOR SIMULATION IN SEMICONDUCTOR DESIGN PROCESS, AND SIMULATION METHOD IN SEMICONDUCTOR DESIGN PROCESS USING THE SAME
NAM, Yunjun, CHOI, Byungseon, HUH, In, CHOE, Jaemyung, MOON, Hyowon, KANG, Bogyeong, JANG, Hyunjae
Year of Publication 24.01.2024
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Year of Publication 24.01.2024
Patent
METHOD AND SYSTEM FOR SIMULATING AND VERIFYING LAYOUT BASED ON DISTRIBUTION
KIM, Younggu, JEONG, Changwook, NAM, Yunjun, HUH, In, CHA, Moonhyun, JANG, Hyunjae, KIM, Jongwon, KIM, Satbyul
Year of Publication 20.07.2023
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Year of Publication 20.07.2023
Patent
SIMULATION SYSTEM FOR SEMICONDUCTOR PROCESS AND SIMULATION METHOD THEREOF
Park, Min-Chul, Jang, Hyunjae, Jeong, Changwook, Noh, Hyeon Kyun, Huh, In, MYUNG, Sanghoon
Year of Publication 11.05.2023
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Year of Publication 11.05.2023
Patent
Simulation system for semiconductor process and simulation method thereof
Park, Min-Chul, Jang, Hyunjae, Jeong, Changwook, Noh, Hyeon Kyun, Huh, In, Myung, Sanghoon
Year of Publication 07.02.2023
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Year of Publication 07.02.2023
Patent
SIMULATION SYSTEM FOR SEMICONDUCTOR PROCESS AND SIMULATION METHOD THEREOF
Jang, Hyunjae, Jeong, Changwook, Noh, Hyeon Kyun, Huh, In, MYUNG, Sanghoon, Park, Min-chul
Year of Publication 27.05.2021
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Year of Publication 27.05.2021
Patent
METHOD AND SYSTEM FOR HYBRID MODEL INCLUDING MACHINE LEARNING MODEL AND RULE-BASED MODEL
Park, Minchul, Jang, Hyunjae, JEONG, Changwook, Huh, In, Myung, Sanghoon, Noh, Hyeonkyun
Year of Publication 25.02.2021
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Year of Publication 25.02.2021
Patent