A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
SOHN, Kyomin, NA, Taesik, LEE, Ki-Won, PARK, Jun-Seok, LEE, Jongeun, LEE, Byunghyun, JUN, Inwoo, PARK, Juseop, PARK, Junghwan, CHOI, Hundai, KIM, Sanghee, CHUNG, Haeyoung, SONG, Indal, CHOI, Young, JUNG, Dae-Hee, KIM, Byungchul, CHOI, Jung-Hwan, JANG, Seong-Jin, KIM, Chi-Wook, LEE, Jung-Bae, JOO SUN CHOI, SHIM, Yong, BAE, Wonil, KANG, Sanghee, LEE, Dongsu, JUNG, Hangyun, HYUN, Seokhun, JEOUNG, Hanki
Published in IEEE journal of solid-state circuits (01.01.2013)
Published in IEEE journal of solid-state circuits (01.01.2013)
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Journal Article
Conference Proceeding
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme
Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki-Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byungsick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo Sun Choi, Kyung Seok Oh
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding