Development of a large-scale TEG for evaluation and analysis of yield and variation
Yamamoto, M., Endo, H., Masuda, H.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
A combined test structure with ring oscillator and inverter chain for evaluating optimum high-speed/low-power operation
Matsuda, T., Iwata, H., Ohzone, T., Yamashita, K., Koike, N., Tatsuuma, K.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
Optimisation of integrated RF varactors on a 0.35 /spl mu/m BiCMOS technology
Kelly, S.C., Power, J.A., O'Neill, M.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
Test time reduction methods for yield test structures
Hess, C., Read, H., Ren, J., Weiland, L.H., Jianjun Cheng, Chock Gan, Karbasi, H., Winters, S.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
An integrated test chip for the complete characterization and monitoring of a 0.25/spl mu/m CMOS technology that fits into five scribe line structures 150/spl mu/m by 5000/spl mu/m
Lefferts, R., Jakubiec, C.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
The negative capacitance effect on the C-V measurement of ultra thin gate dielectrics induced by the stray capacitance of the measurement system
Okawa, Y., Norimatsu, H., Suto, H., Takayanagi, M.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
Characterization and modeling of MOSFET mismatch of a deep submicron technology
Quarantelli, M., Saxena, S., Dragone, N., Babcock, J.A., Hess, C., Minehane, S., Winters, S., Jianjun Chen, Karbasi, H., Guardiani, C.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
Substrate resistance modeling for noise coupling analysis
Kristiansson, S., Kagganti, S.P., Ewert, T., Ingvarson, F., Olsson, J., Jeppson, K.O.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
A test circuit for measuring MOSFET threshold voltage mismatch
Terada, K., Eimitsu, M.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding
Study on STI mechanical stress induced variations on advanced CMOSFETs
Sheu, Y.M., Doong, K.Y.Y., Lee, C.H., Chen, M.J., Diaz, C.H.
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
Published in International Conference on Microelectronic Test Structures, 2003 (2003)
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Conference Proceeding