Search Results - "Il-Gweon Kim" :: K.UTB vyhledávací portál

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Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact

by Il-Gweon Kim, Yanagidaira, K., Hiramoto, T.
Published in IEEE electron device letters (01.05.2004)

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Real impact of dynamic operation stress during burn-in on DRAM retention time

by Kim, I.-G., Choi, S.-K., Choi, J.-H., Park, J.-S.
Published in IEEE transactions on electron devices (01.04.2004)

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Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory

by Kim, Nam-Sung, Kim, Il-Gweon, Kwon, Tae-Seok, Park, Joo-Seog
Published in Japanese Journal of Applied Physics (01.11.2003)

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Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells

by Kim, Nam-Sung, Kim, Il-Gweon, Choy, Jun-Ho, Park, Joo-Seog
Published in Japanese Journal of Applied Physics (01.04.2002)

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DRAM Reliability Degradation By Dynamic Operation Stress During Burn-In

by Kim, Il-Gweon, Kim, Nam-Sung, Park, Joo-Seog
Published in Japanese Journal of Applied Physics (2003)

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IMPACT OF NF3-ADDED INTERLAYER DIELECTRIC HIGH DENSITY PLASMA PROCESS ON HUMP EFFECT IN SUBMICRON N-TYPE METAL OXIDE SILICON FIELD EFFECT TRANSISTOR

by Park, J-S, Kim, I-G, Kim, Y-S
Published in Japanese Journal of Applied Physics, Part 1 (2003)

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Low-Damage Gate Etching with High Degree of Anisotropy in High-Density DRAM Cell

by Kim, Il-Gweon, Kim, Nam-Sung, Park, Joo-Seog, Park, Dae-Young
Published in Japanese Journal of Applied Physics (01.04.2002)

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Suppression of Anomalous Edge Channel Effect for 0.15 µm DRAM Cell and Beyond

by Kim, Il-Gweon, Choi, Se-Kyeong, Park, Joo-Seog
Published in Japanese Journal of Applied Physics (30.04.2003)

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A Metal Dual Work-Function Gate (MDWG) for the Continuous Scaling of DRAM Cell Transistors

by Kim, Junsoo, Lee, Hyun Jung, Jang, Sung Ho, Lee, Jun Bum, Kim, Il Gweon, Oh, Jeonghoon, Park, Jemin, Song, Jaihyuk
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)

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Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell

by KIM, Il-Gweon, KIM, Nam-Sung, CHOI, Se-Kyeong, YOUN, Tae-Un, JUNG, Hyuck-Chai, KWEON, Jae-Soon, CHUN, Young-Il, KIM, Wan-Soo, BONG, Myung-Jong, PARK, Joo-Seog
Published in Digest. International Electron Devices Meeting (2002)

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DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode

by Il-Gweon Kim, Se-Kyeong Choi, Jin-Hyeok Choi, Joo-Seog Park
Published in 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual (2003)

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Improvement of the short channel effect in PMOSFETs using cold implantation

by Lee, Suk Hun, Park, Se Geun, Jeong, Seong Hoon, Jung, Hyuck-Chai, Kim, Il Gweon, Kang, Dong-Ho, Nam, Hyo-Jik, Kim, Dae Jung, Lee, Kyu Pil, Choi, Joo Sun, Jung, Woosuk, Park, Yongkook, Choi, Changhwan, Park, Jin-Hong
Published in Materials research bulletin (01.10.2016)

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Suppression of boron diffusion using carbon co-implantation in DRAM

by Lee, Suk Hun, Park, Se Geun, Kim, Shin Deuk, Jung, Hyuck-Chai, Kim, Il Gweon, Kang, Dong-Ho, Kim, Dae Jung, Lee, Kyu Pil, Choi, Joo Sun, Baek, Jung-Woo, Choi, Moonsuk, Park, Yongkook, Choi, Changhwan, Park, Jin-Hong
Published in Materials research bulletin (01.10.2016)

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Real impact of W/WNx/Poly-Si gate stack in volume production of high density DRAM

by Il-Gweon Kim, Nam-Sung Kim, Jun-Ho Choy, Byung-Hak Lee, Yong-Gue Sung, Jong-Hwan Kim, Jin-Hee Cho, Dong-Chan Kim, Kee-Soo Kim, Jo-Bong Choi, Se-Kyoung Choi, Young-Woo Kweon, Ho-Yup Kwon, Dae-Guy Park, Joo-Seog Park, Dae-Young Park
Published in International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) (2001)

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