Search Results - "IPSJ Transactions on System LSI Design Methodology" :: K.UTB vyhledávací portál

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Polygon Fracture Method Considering Maximum Shot Size for Variable Shaped-beam Mask Writing

by Hasegawa, Mitsuru, Matsuzaki, Taiki, Fujiyoshi, Kunihiro
Published in IPSJ Transactions on System and LSI Design Methodology (2025)

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Message from the Editor-in-Chief

by Ishihara, Tohru
Published in IPSJ Transactions on System and LSI Design Methodology (2025)

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Scalar Replacement in the Presence of Multiple Write Accesses with Non-constant Reuse Distances

by Seto, Kenshu
Published in IPSJ Transactions on System and LSI Design Methodology (2025)

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1W8R 20T SRAM Codebook for 20% Energy Reduction in Mixed-precision Deep-learning Inference Processor System

by Ohara, Ryotaro, Masaya, Kabuto, Fukunaga, Atsushi, Taichi, Masakazu, Yasuda, Yuto, Hamabe, Riku, Izumi, Shintaro, Kawaguchi, Hiroshi
Published in IPSJ Transactions on System and LSI Design Methodology (2025)

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Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP

by Hiraga, Keizo, Seto, Kenshu, Bessho, Kazuhiro, Iida, Masahiro
Published in IPSJ Transactions on System and LSI Design Methodology (2025)

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Design of Synthesizable Digital Phase Locked Loops

by Zhang, Yuncheng, Okada, Kenichi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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Slashing IC Power and Democratizing IC Access for the Digital Age

by Kuroda, Tadahiro
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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A Case Study for Improving Performances of Deep-Learning Processor with MRAM

by Ohara, Ryotaro, Fukunaga, Atsushi, Taichi, Masakazu, Kabuto, Masaya, Hamabe, Riku, Ikegawa, Masato, Izumi, Shintaro, Kawaguchi, Hiroshi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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A Learning-based Control Scheme for MTJ-based Non-volatile Flip-Flops

by Nakabeppu, Shota, Yamasaki, Nobuyuki
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V

by Wang, Hansen, Li, Dongju, Isshiki, Tsuyoshi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

by Kitamura, Takehiro, Hisakado, Takashi, Wada, Osami, Islam, Mahfuzul
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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Power Optimized Design Framework for FPGA Clusters

by Iizuka, Kensuke, Ito, Kohei, Yasudo, Ryota, Amano, Hideharu
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

by Knechtel, Johann, Sinanoglu, Ozgur, Elfadel, Ibrahim (Abe) M., Lienig, Jens, Sze, Cliff C. N.
Published in IPSJ Transactions on System LSI Design Methodology (01.01.2017)

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Measurement Results of Real Circuit Delay Degradation under Realistic Workload

by Shimamura, Kotaro, Takehara, Takeshi, Ikeda, Naohiro
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2023)

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Computational Lithography Using Machine Learning Models

by Shin, Youngsoo
Published in IPSJ Transactions on System LSI Design Methodology (2021)

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LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure

by Sadasue, Tamon, Isshiki, Tsuyoshi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2023)

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A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor

by Tanaka, Ippei, Miyagawa, Naoyuki, Kimura, Tomoya, Imagawa, Takashi, Ochi, Hiroyuki
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2023)

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Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage

by Hamaguchi, Kiyoharu
Published in IPSJ Transactions on System and LSI Design Methodology (2023)

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Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection

by Kataoka, Gaku, Yamamoto, Masahiro, Inagi, Masato, Nagayama, Shinobu, Wakabayashi, Shin'ichi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2023)

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A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks

by Nakahara, Yasuhiro, Masuda, Yuta, Kiyama, Masato, Amagasaki, Motoki, Iida, Masahiro
Published in IPSJ Transactions on System LSI Design Methodology (01.01.2022)

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