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DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator
Li, Shang, Yang, Zhiyuan, Reddy, Dhiraj, Srivastava, Ankur, Jacob, Bruce
Published in IEEE computer architecture letters (01.07.2020)
Published in IEEE computer architecture letters (01.07.2020)
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Characterizing and Understanding GCNs on GPU
Yan, Mingyu, Chen, Zhaodong, Deng, Lei, Ye, Xiaochun, Zhang, Zhimin, Fan, Dongrui, Xie, Yuan
Published in IEEE computer architecture letters (01.01.2020)
Published in IEEE computer architecture letters (01.01.2020)
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DRAMSim2: A Cycle Accurate Memory System Simulator
Rosenfeld, P, Cooper-Balis, E, Jacob, B
Published in IEEE computer architecture letters (01.01.2011)
Published in IEEE computer architecture letters (01.01.2011)
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Fast Bulk Bitwise AND and OR in DRAM
Seshadri, Vivek, Hsieh, Kevin, Boroum, Amirali, Donghyuk Lee, Kozuch, Michael A., Mutlu, Onur, Gibbons, Phillip B., Mowry, Todd C.
Published in IEEE computer architecture letters (01.07.2015)
Published in IEEE computer architecture letters (01.07.2015)
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gem5-gpu: A Heterogeneous CPU-GPU Simulator
Power, Jason, Hestness, Joel, Orr, Marc S., Hill, Mark D., Wood, David A.
Published in IEEE computer architecture letters (01.01.2015)
Published in IEEE computer architecture letters (01.01.2015)
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Architectural Implications of Graph Neural Networks
Zhang, Zhihui, Leng, Jingwen, Ma, Lingxiao, Miao, Youshan, Li, Chao, Guo, Minyi
Published in IEEE computer architecture letters (01.01.2020)
Published in IEEE computer architecture letters (01.01.2020)
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Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference
Liu, Zhi-Gang, Whatmough, Paul N., Mattina, Matthew
Published in IEEE computer architecture letters (01.01.2020)
Published in IEEE computer architecture letters (01.01.2020)
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LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
Boroumand, Amirali, Ghose, Saugata, Patel, Minesh, Hassan, Hasan, Lucia, Brandon, Hsieh, Kevin, Malladi, Krishna T., Hongzhong Zheng, Mutlu, Onur
Published in IEEE computer architecture letters (01.01.2017)
Published in IEEE computer architecture letters (01.01.2017)
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SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD
Lee, Joo Hwan, Zhang, Hui, Lagrange, Veronica, Krishnamoorthy, Praveen, Zhao, Xiaodong, Ki, Yang Seok
Published in IEEE computer architecture letters (01.07.2020)
Published in IEEE computer architecture letters (01.07.2020)
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Characterizing and Understanding HGNNs on GPUs
Yan, Mingyu, Zou, Mo, Yang, Xiaocheng, Li, Wenming, Ye, Xiaochun, Fan, Dongrui, Xie, Yuan
Published in IEEE computer architecture letters (01.07.2022)
Published in IEEE computer architecture letters (01.07.2022)
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Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator
Lucas, Benjamin J., Alwan, Ali, Murzello, Marion, Tu, Yazheng, He, Pengzhou, Schwartz, Andrew J., Guevara, David, Guin, Ujjwal, Juretus, Kyle, Xie, Jiafeng
Published in IEEE computer architecture letters (01.01.2022)
Published in IEEE computer architecture letters (01.01.2022)
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RAMBO: Resource Allocation for Microservices Using Bayesian Optimization
Li, Qian, Li, Bin, Mercati, Pietro, Illikkal, Ramesh, Tai, Charlie, Kishinevsky, Michael, Kozyrakis, Christos
Published in IEEE computer architecture letters (01.01.2021)
Published in IEEE computer architecture letters (01.01.2021)
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Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
Luo, Haocong, Tugrul, Yahya Can, Bostanc, F. Nisa, Olgun, Ataberk, Yaglkc, A. Giray, Mutlu, Onur
Published in IEEE computer architecture letters (01.01.2024)
Published in IEEE computer architecture letters (01.01.2024)
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Architectural Support for Mitigating Row Hammering in DRAM Memories
Dae-Hyun Kim, Nair, Prashant J., Qureshi, Moinuddin K.
Published in IEEE computer architecture letters (01.01.2015)
Published in IEEE computer architecture letters (01.01.2015)
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A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing
Balaji, Adarsha, Song, Shihao, Das, Anup, Dutt, Nikil, Krichmar, Jeff, Kandasamy, Nagarajan, Catthoor, Francky
Published in IEEE computer architecture letters (01.07.2019)
Published in IEEE computer architecture letters (01.07.2019)
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GPU-NEST: Characterizing Energy Efficiency of Multi-GPU Inference Servers
Jahanshahi, Ali, Sabzi, Hadi Zamani, Lau, Chester, Wong, Daniel
Published in IEEE computer architecture letters (01.07.2020)
Published in IEEE computer architecture letters (01.07.2020)
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