A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit
YANG, Rong-Jyi, CHAO, Kuan-Hua, HWU, Sy-Chyuan, LIANG, Chuan-Kang, LIU, Shen-Iuan
Published in IEEE journal of solid-state circuits (01.06.2006)
Published in IEEE journal of solid-state circuits (01.06.2006)
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Journal Article
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
LIANG, Che-Fu, HWU, Sy-Chyuan, LIU, Shen-Iuan
Published in IEEE journal of solid-state circuits (01.05.2008)
Published in IEEE journal of solid-state circuits (01.05.2008)
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Journal Article
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
Published in IEEE Custom Integrated Circuits Conference 2006 (01.09.2006)
Published in IEEE Custom Integrated Circuits Conference 2006 (01.09.2006)
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Conference Proceeding
A receiver architecture for intra-band carrier aggregation
Sy-Chyuan Hwu, Razavi, Behzad
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01.06.2014)
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Conference Proceeding
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
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Conference Proceeding
A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
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Conference Proceeding
A reference-free, digital background calibration technique for gated-oscillator-based CDR/PLL
Liang, Che-Fu, Hwu, Sy-Chyuan, Tu, Yu-Hsuan, Yang, Ya-Lun, Li, Hung-Sung
Published in 2009 Symposium on VLSI Circuits (01.06.2009)
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Published in 2009 Symposium on VLSI Circuits (01.06.2009)
Conference Proceeding