The Complementary FET (CFET) for CMOS scaling beyond N3
Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., Demuynck, S., Bao, T. Huynh, Veloso, A., Horiguchi, N., Mocuta, A., Mocuta, D., Boemmels, J.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Conference Proceeding
Vertical device architecture for 5nm and beyond: Device & circuit implications
Thean, A. V.-Y, Yakimets, D., Huynh Bao, T., Schuddinck, P., Sakhare, S., Bardon, M. Garcia, Sibaja-Hernandez, A., Ciofi, I., Eneman, G., Veloso, A., Ryckaert, J., Raghavan, P., Mercha, A., Mocuta, A., Tokei, Z., Verkest, D., Wambacq, P., De Meyer, K., Collaert, N.
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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Conference Proceeding
Journal Article
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
Veloso, A., Huynh-Bao, T., Matagne, P., Jang, D., Eneman, G., Horiguchi, N., Ryckaert, J.
Published in Solid-state electronics (01.06.2020)
Published in Solid-state electronics (01.06.2020)
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Journal Article
Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits
Veloso, A., Hikavyy, A., Loo, R., Paraschiv, V., Chan, B. T., Radisic, D., Li, W., Versluijs, J. J., Teugels, L., Sebaai, F., Favia, P., Eneman, G., Bender, H., Vancoille, E., Scheerder, J. E., Fleischmann, C., Horiguchi, N., Matagne, P., Huynh-Bao, T., Chasin, A., Simoen, E., Vecchio, E., Devriendt, K., Brus, S., Rosseel, E.
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
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Conference Proceeding
Nanowire & Nanosheet Fets for Advanced Ultra-Scaled, High-Density Logic and Memory Applications
Veloso, A., Matagne, P., Eneman, G., Jang, D., Huynh-Bao, T., Chasin, A., Simoen, E., De Keersgieter, A., Horiguchi, N.
Published in 2020 China Semiconductor Technology International Conference (CSTIC) (26.06.2020)
Published in 2020 China Semiconductor Technology International Conference (CSTIC) (26.06.2020)
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Conference Proceeding
Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory Applications
Veloso, A., Huynh-Bao, T., Matagne, P., Jang, D., Horiguchi, N., Ryckaert, J., Mocuta, D.
Published in 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) (01.04.2019)
Published in 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) (01.04.2019)
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Conference Proceeding
(Invited) Vertical Nanowire FET Integration and Device Aspects
Veloso, Anabela, Altamirano-Sánchez, Efraín, Brus, Stephan, Chan, B. T., Cupak, Miroslav, Dehan, Morin, Delvaux, Christie, Devriendt, Katia, Eneman, Geert, Ercken, Monique, Huynh-Bao, Trong, Ivanov, Tsvetan, Matagne, Philippe, Merckling, Clement, Paraschiv, Vasile, Ramesh, Siva, Rosseel, Erik, Rynders, Luc, Sibaja-Hernandez, Arturo, Suhard, Samuel, Tao, Zheng, Vecchio, Emma, Waldron, Niamh, Yakimets, Dmitry, De Meyer, Kristin, Mocuta, Dan, Collaert, Nadine, Thean, Aaron
Published in ECS transactions (04.05.2016)
Published in ECS transactions (04.05.2016)
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Journal Article
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Veloso, A., Parvais, B., Matagne, P., Simoen, E., Huynh-Bao, T., Paraschiv, V., Vecchio, E., Devriendt, K., Rosseel, E., Ercken, M., Chan, B. T., Delvaux, C., Altamirano-Sanchez, E., Versluijs, J. J., Tao, Z., Suhard, S., Brus, S., Sibaja-Hernandez, A., Waldron, N., Lagrain, P., Richard, O., Bender, H., Chasin, A., Kaczer, B., Ivanov, T., Ramesh, S., De Meyer, K., Ryckaert, J., Collaert, N., Thean, A.
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Conference Proceeding
12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices
Kim, M.-S., Harada, N., Kikuchi, Y., Boemmels, J., Mitard, J., Huynh-Bao, T., Matagne, P., Tao, Z., Li, W., Devriendt, K., Ragnarsson, L.-A., Lorant, C., Sebaai, F., Porret, C., Rosseel, E., Dangol, A., Batuk, D., Martinez-Alanis, G., Geypen, J., Jourdan, N., Sepulveda, A., Puliyalil, H., Jamieson, G., van der Veen, M., Teugels, L., El-Mekki, Z., Altamirano-Sanchez, E., Li, Y., Nakamura, H., Mocuta, D., Masuoka, F.
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Bao, T. Huynh, Yakimets, D., Ryckaert, J., Ciofi, I., Baert, R., Veloso, A., Boemmels, J., Collaert, N., Roussel, P., Demuynck, S., Raghavan, P., Mercha, A., Tokei, Z., Verkest, D., Thean, A. V-Y, Wambacq, P.
Published in 2014 44th European Solid State Device Research Conference (ESSDERC) (01.09.2014)
Published in 2014 44th European Solid State Device Research Conference (ESSDERC) (01.09.2014)
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Conference Proceeding
(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs
Veloso, Anabela, Paraschiv, Vasile, Vecchio, Emma, Devriendt, Katia, Li, Waikin, Simoen, Eddy, Chan, B. T., Tao, Zheng, Rosseel, Erik, Loo, Roger, Milenin, Alexey P., Kunert, Bernardette, Teugels, Lieve, Sebaai, Farid, Lorant, Christophe, van Dorp, Dennis, Altamirano-Sánchez, Efraín, Brus, Stephan, Marien, Philippe, Fleischmann, Claudia, Melkonyan, Davit, Huynh-Bao, Trong, Eneman, Geert, Hellings, Geert, Sibaja-Hernandez, Arturo, Matagne, Philippe, Waldron, Niamh, Mocuta, Dan, Collaert, Nadine
Published in ECS transactions (15.08.2017)
Published in ECS transactions (15.08.2017)
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Journal Article
Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
Yakimets, D., Bao, T. Huynh, Bardon, M. Garcia, Dehan, M., Collaert, N., Mercha, A., Tokei, Z., Thean, A., Verkest, D., De Meyer, K.
Published in 72nd Device Research Conference (01.06.2014)
Published in 72nd Device Research Conference (01.06.2014)
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Conference Proceeding
DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM
Matagne, P., Nakamura, H., Kim, M.-S., Kikuchi, Y., Huynh-Bao, T., Tao, Z., Li, W., Devriendt, K., Ragnarsson, L.-A., Boemmels, J., Mallik, A., Altamirano-Sachez, E., Sebaai, F., Lorant, C., Jourdan, N., Porret, C., Mocuta, D., Harada, N., Masuoka, F.
Published in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2018)
Published in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2018)
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Conference Proceeding
(Invited) Heterogeneous Nano- to Wide-Scale Co-Integration of Beyond-Si and Si CMOS Devices to Enhance Future Electronics
Thean, Aaron, Collaert, Nadine, Radu, Iuliana P., Waldron, Niamh, Merckling, Clement, Witters, Liesbeth, Loo, Roger, Mitard, Jerome, Rooyackers, Rita, Vandooren, Anne, Verhulst, A., Veloso, Anabela, Yakimets, D., Bao, T. Huynh, Chiappe, Danielle, Vaysset, A., Zografos, O., Caymax, Matty, Huyghebaert, C, Barla, Kathy, Steegen, A.
Published in ECS transactions (31.03.2015)
Published in ECS transactions (31.03.2015)
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Journal Article
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
Sakhare, S., Perumkunnil, M., Bao, T. Huynh, Rao, S., Kim, W., Crotti, D., Yasin, F., Couet, S., Swerts, J., Kundu, S., Yakimets, D., Baert, R., Oh, HR, Spessot, A., Mocuta, A., Kar, G. Sankar, Furnemont, A.
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
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Conference Proceeding
SRAM designs for 5nm node and beyond: Opportunities and challenges
Huynh-Bao, T., Sakhare, S., Ryckaert, J., Spessot, A., Verkest, D., Mocuta, A.
Published in 2017 IEEE International Conference on IC Design and Technology (ICICDT) (01.05.2017)
Published in 2017 IEEE International Conference on IC Design and Technology (ICICDT) (01.05.2017)
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Conference Proceeding
Vertical devices for future nano-electronic applications
Collaert, N., Veloso, A., Huynh-Bao, T., Yakimets, D., Ivanov, Ts, Ramesh, S., Matagne, P., Sibaja-Hernandez, A., Liu, Z., Merckling, C., Waldron, N., Thean, A.
Published in 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC) (01.10.2016)
Published in 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC) (01.10.2016)
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Conference Proceeding
Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Veloso, A., Tao, Z., Li, W., Altamirano-Sanchez, E., Versluijs, J. J., Brus, S., Matagne, P., Waldron, N., Ryckaert, J., Mocuta, D., Collaert, N., Huynh-Bao, T., Rosseel, E., Paraschiv, V., Devriendt, K., Vecchio, E., Delvaux, C., Chan, B. T., Ercken, M.
Published in 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2016)
Published in 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2016)
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Conference Proceeding
(Invited) Heterogeneous Nano- to Wide-Scale Co-Integration of Beyond-Si and Si CMOS Devices to Enhance Future Electronics
Thean, Aaron, Collaert, Nadine, Radu, Iuliana P., Waldron, Niamh, Merckling, Clement, Witters, Liesbeth, Loo, Roger, Mitard, Jerome, Rooyackers, Rita, Vandooren, Anne, Verhulst, A., Veloso, Anabela, Yakimets, D., Bao, T. Huynh, Chiappe, Danielle, Vaysset, A., Zografos, O., Caymax, Matty, Huyghebaert, C, Barla, Kathy, Steegen, A.
Published in Meeting abstracts (Electrochemical Society) (29.04.2015)
Published in Meeting abstracts (Electrochemical Society) (29.04.2015)
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Journal Article