A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
Harwood, Mike, Warke, Nirmal, Simpson, Richard, Leslie, Tom, Amerasekera, Ajith, Batty, Sean, Colman, Derek, Carr, Eugenia, Gopinathan, Venu, Hubbins, Steve, Hunt, Peter, Joy, Andy, Khandelwal, Pulkit, Killips, Bob, Krause, Thomas, Lytollis, Shaun, Pickering, Andy, Saxton, Mark, Sebastio, David, Swanson, Graeme, Szczepanek, Andre, Ward, Terry, Williams, Jeff, Williams, Richard, Willwerth, Tom
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
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