Search Results - "Hsinyu Tsai" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges

by Mackin, Charles, Narayanan, Pritish, Ambrogio, Stefano, Tsai, Hsinyu, Spoon, Katie, Fasoli, Andrea, Chen, An, Friz, Alexander, Shelby, Robert M., Burr, Geoffrey W.
Published in 2020 IEEE International Reliability Physics Symposium (IRPS) (01.04.2020)

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Conference Proceeding

Optimization of Analog Accelerators for Deep Neural Networks Inference

Optimization of Analog Accelerators for Deep Neural Networks Inference

by Fasoli, Andrea, Ambrogio, Stefano, Narayanan, Pritish, Tsai, Hsinyu, Mackin, Charles, Spoon, Katherine, Friz, Alexander, Chen, An, Burr, Geoffrey W.
Published in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (01.10.2020)

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Conference Proceeding

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)

by Frank, Martin M., Li, Ning, Rasch, Malte J., Jain, Shubham, Chen, Ching-Tzu, Muralidhar, Ramachandran, Han, Jin-Ping, Narayanan, Vijay, Philip, Timothy M., Brew, Kevin, Simon, Andrew, Saraf, Iqbal, Saulnier, Nicole, Boybat, Irem, Wozniak, Stanislaw, Sebastian, Abu, Narayanan, Pritish, Mackin, Charles, Chen, An, Tsai, Hsinyu, Burr, Geoffrey W.
Published in 2023 IEEE International Reliability Physics Symposium (IRPS) (01.03.2023)

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Conference Proceeding

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited)

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited)

by Hosokawa, Kohji, Narayanan, Pritish, Ambrogio, Stefano, Tsai, Hsinyu, Mackin, Charles, Fasoli, Andrea, Friz, Alexander, Chen, An, Luquin, Jose, Spoon, Katherine, Burr, Geoffrey W., Lewis, Scott C.
Published in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2021)

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Conference Proceeding

Drift regularization to counteract variation in drift coefficients for analog accelerators

Drift regularization to counteract variation in drift coefficients for analog accelerators

by TSAI, HsinYu, KARIYAPPA, Sanjay
Year of Publication 27.04.2023

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Patent

Drift regularization to counteract variation in drift coefficients for analog accelerators

Drift regularization to counteract variation in drift coefficients for analog accelerators

by Sanjay Kariyappa, HsinYu Tsai
Year of Publication 01.01.2023

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Patent

Drift regularization to counteract variation in drift coefficients for analog accelerators

Drift regularization to counteract variation in drift coefficients for analog accelerators

by Kariyappa, Sanjay, Tsai, Hsinyu
Year of Publication 29.11.2022

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Patent

Drift regularization to counteract variation in drift coefficients for analog accelerators

Drift regularization to counteract variation in drift coefficients for analog accelerators

by TSAI, HsinYu, KARIYAPPA, Sanjay
Year of Publication 17.11.2022

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Patent

DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS

DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS

by TSAI, HSINYU, KARIYAPPA, SANJAY
Year of Publication 23.12.2021

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Patent

DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS

DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS

by TSAI, HsinYu, KARIYAPPA, Sanjay
Year of Publication 23.12.2021

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Patent

DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS

DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS

by Tsai, HsinYu, Kariyappa, Sanjay
Year of Publication 23.12.2021

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Patent

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

by Burr, Geoffrey, Narayanan, Pritish, Tsai, HsinYu
Year of Publication 09.01.2024

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Patent

(Invited) Emerging Nonvolatile Memories for Analog Neuromorphic Computing

(Invited) Emerging Nonvolatile Memories for Analog Neuromorphic Computing

by Chen, An, Ambrogio, Stefano, Narayanan, Pritish, Okazaki, Atsuya, Tsai, Hsinyu, Hosokawa, Kohji, Mackin, Charles, Nomura, Akiyo, Friz, Alexander, Fasoli, Andrea, Luquin, Jose, Burr, Geoffrey
Published in Meeting abstracts (Electrochemical Society) (09.08.2024)

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Journal Article

ORGANIZING SEQUENCES FOR TRANSFORMER COMPUTE

ORGANIZING SEQUENCES FOR TRANSFORMER COMPUTE

by Burr, Geoffrey, Tsai, HsinYu, Jain, Shubham
Year of Publication 01.06.2023

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Patent

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

by NARAYANAN, Pritish, TSAI, Hsinyu, BURR, Geoffrey
Year of Publication 27.04.2023

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Patent

EFFICIENT TILE MAPPING FOR ROW-BY-ROW CONVOLUTIONAL NEURAL NETWORK MAPPING FOR ANALOG ARTIFICIAL INTELLIGENCE NETWORK INFERENCE

EFFICIENT TILE MAPPING FOR ROW-BY-ROW CONVOLUTIONAL NEURAL NETWORK MAPPING FOR ANALOG ARTIFICIAL INTELLIGENCE NETWORK INFERENCE

by Burr, Geoffrey, Narayanan, Pritish, Tsai, HsinYu
Year of Publication 30.03.2023

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Patent

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

by Pritish Narayanan, Geoffrey Burr, Hsinyu Tsai
Year of Publication 15.03.2023

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Patent

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

by Burr, Geoffrey, Narayanan, Pritish, Tsai, Hsinyu
Year of Publication 24.01.2023

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Patent

IMPLICIT VECTOR CONCATENATION WITHIN 2D MESH ROUTING

IMPLICIT VECTOR CONCATENATION WITHIN 2D MESH ROUTING

by HOSOKAWA, Kohji, JAIN, Shubham, TSAI, HsinYu, NARAYANAN, Pritish, BURR, Geoffrey
Year of Publication 07.08.2024

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Patent

Row-by-row convolutional neural network mapping for analog artificial intelligence network training

Row-by-row convolutional neural network mapping for analog artificial intelligence network training

by Rasch, Malte Johannes, Burr, Geoffrey, Narayanan, Pritish, Tsai, Hsinyu
Year of Publication 30.07.2024

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Patent

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