Electrical and Reliability Characteristics of FinFETs With High-k Gate Stack and Plasma Treatments
Li, Yan-Lin, Chang-Liao, Kuei-Shu, Li, Chen-Chien, Huang, Chin-Hsiu, Tsai, Shang-Fu, Li, Cheng-Yuan, Hong, Zi-Qin, Fang, Hsin-Kai
Published in IEEE transactions on electron devices (01.01.2021)
Published in IEEE transactions on electron devices (01.01.2021)
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Journal Article
Impacts of Electrical Field in Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Device
Fang, Hsin-Kai, Chang-Liao, Kuei-Shu, Chou, Kuan-Chi, Chao, Tzu-Cheng, Tsai, Jung-En, Li, Yan-Lin, Huang, Wen-Hsien, Shen, Chang-Hong, Shieh, Jia-Min
Published in IEEE electron device letters (01.12.2020)
Published in IEEE electron device letters (01.12.2020)
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Journal Article
Operation Characteristics of Gate-All-Around Junctionless Flash Memory Devices With Si₃N₄/ZrO-Based Stacked Trapping Layer
Fang, Hsin-Kai, Chang-Liao, Kuei-Shu, Cheng, Chia-Hsin, Lu, Yu-Chin, Huang, Wen-Hsien, Shen, Chang-Hong, Shieh, Jia-Min
Published in IEEE transactions on electron devices (01.09.2020)
Published in IEEE transactions on electron devices (01.09.2020)
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Journal Article
Operation characteristics of Poly-Si nanowire charge-trapping flash memory devices with SiGe and Ge buried channels
Fang, Hsin-Kai, Chang-Liao, Kuei-Shu, Huang, Chien-Pang, Lee, Wei-Zhi
Published in Vacuum (01.06.2017)
Published in Vacuum (01.06.2017)
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Journal Article
Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device With Ge Channel
Ye, Zong-Hao, Chang-Liao, Kuei-Shu, Liu, Li-Jung, Cheng, Jen-Wei, Fang, Hsin-Kai
Published in IEEE electron device letters (01.12.2015)
Published in IEEE electron device letters (01.12.2015)
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Journal Article
SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices
Fang, Hsin-Kai, Chang-Liao, Kuei-Shu, Cheng, Chia-Hsin, Lin, Po-Yao, Huang, Wen-Hsien, Shen, Chang-Hong, Shieh, Jia-Min
Published in Microelectronics and reliability (01.12.2018)
Published in Microelectronics and reliability (01.12.2018)
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Journal Article
Minimized program disturb for vertically stacked junctionless charge-trapping flash memory devices by adopting in-situ doped poly-silicon channel
Fang, Hsin-Kai, Chang-Liao, Kuei-Shu, Chen, Chun-Yuan, Chen, Po-Hao, Li, Dong-Yan, Huang, Chien-Pang, Shen, Chang-Hong, Shieh, Jia-Min
Published in Microelectronic engineering (01.11.2015)
Published in Microelectronic engineering (01.11.2015)
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Journal Article
Very low EOT and high oxidation state interfacial layer in Ge MOS devices
Szu-Chun Yu, Kuei-Shu Chang-Liao, Mong-Chi Li, Wei-Fong Chi, Chen-Chien Li, Li-Jung Liu, Tzu-Min Lee, Yu-Wei Chang, Hsin-Kai Fang, Chung-Hao Fu, Chun-Chang Lu, Zong-Hao Ye, Tien-Ko Wang
Published in 2014 Silicon Nanoelectronics Workshop (SNW) (01.06.2014)
Published in 2014 Silicon Nanoelectronics Workshop (SNW) (01.06.2014)
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Conference Proceeding
Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
Tsai, Jung-En, Chang-Liao, Kuei-Shu, Fang, Hsin-Kai
Published in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (19.04.2021)
Published in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (19.04.2021)
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Conference Proceeding