Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process
Hsia, Chu-En, Chang, Chin-Ho, Chen, Yung-Shun, Lai, Po-Yu, Jen, Ching Lin, Peng, Yung-Chow, Li, Shenggao
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)
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