13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction
Seo, Yangho, Choi, Jihee, Cho, Sunki, Han, Hyunwook, Kim, Wonjong, Ryu, Gyeongha, Ahn, Jungil, Cho, Younga, Choi, Sungphil, Lee, Seohee, Lee, Wooju, Lee, Chaehyuk, Kim, Kiup, Lee, Seongseop, Park, Sangbeom, Choi, Minjun, Lee, Sungwoo, Kim, Mino, Shin, Taekyun, Jeong, Hyeongsoo, Kim, Hyunseung, Song, Houk, Hong, Yunsuk, Yoon, Seokju, Park, Giwook, You, Hokeun, Choi, Changkyu, Jung, Hae-Kang, Cho, Joohwan, Kim, Jonghwan
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
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