Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy
Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Hu, C., Liu, T.-J.K.
Published in IEEE transactions on electron devices (01.10.2008)
Published in IEEE transactions on electron devices (01.10.2008)
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Journal Article
Influence of multi-hit capability on quantitative measurement of NiPtSi thin film with laser-assisted atom probe tomography
Kinno, T., Akutsu, H., Tomita, M., Kawanaka, S., Sonehara, T., Hokazono, A., Renaud, L., Martin, I., Benbalagh, R., Sallé, B., Takeno, S.
Published in Applied surface science (15.10.2012)
Published in Applied surface science (15.10.2012)
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Journal Article
MOSFET hot-carrier reliability improvement by forward-body bias
Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Chenming Hu, Tsu-Jae King Liu
Published in IEEE electron device letters (01.07.2006)
Published in IEEE electron device letters (01.07.2006)
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Journal Article
MOSFET design for forward body biasing scheme
Hokazono, A., Balasubramanian, S., Ishimaru, K., Ishiuchi, H., Tsu-Jae King Liu, Chenming Hu
Published in IEEE electron device letters (01.05.2006)
Published in IEEE electron device letters (01.05.2006)
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Journal Article
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
Inaba, S., Okano, K., Matsuda, S., Fujiwara, M., Hokazono, A., Adachi, K., Ohuchi, K., Suto, H., Fukui, H., Shimizu, T., Mori, S., Oguma, H., Murakoshi, A., Itani, T., Iinuma, T., Kudo, T., Shibata, H., Taniguchi, S., Takayanagi, M., Azuma, A., Oyamatsu, H., Suguro, K., Katsumata, Y., Toyoshima, Y., Ishiuchi, H.
Published in IEEE transactions on electron devices (01.12.2002)
Published in IEEE transactions on electron devices (01.12.2002)
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Journal Article
Enhancement/depletion MESFETs of diamond and their logic circuits
Hokazono, A., Ishikura, T., Nakamura, K., Yamashita, S., Kawarada, H.
Published in Diamond and related materials (01.03.1997)
Published in Diamond and related materials (01.03.1997)
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Journal Article
Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond
Hokazono, A., Itokawa, H., Kusunoki, N., Mizushima, I., Inaba, S., Kawanaka, S., Toyoshima, Y.
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Published in 2008 Symposium on VLSI Technology (01.06.2008)
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Conference Proceeding
SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology
Inaba, S., Miyano, K., Nagano, H., Hokazono, A., Ohuchi, K., Mizushima, I., Oyamatsu, H., Tsunashima, Y., Ishimaru, K., Toyoshima, Y., Ishiuchi, H.
Published in IEEE transactions on electron devices (01.09.2004)
Published in IEEE transactions on electron devices (01.09.2004)
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Journal Article
150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET
Miyata, T., Tanaka, H., Kagimoto, K., Kamiyashiki, M., Kamimura, M., Hidaka, A., Goto, M., Adachi, K., Hokazono, A., Ohguro, T., Nagaoka, K., Watanabe, Y., Hirooka, S., Ito, Y., Kawanaka, S., Ishimaru, K.
Published in 2015 IEEE International Electron Devices Meeting (IEDM) (01.12.2015)
Published in 2015 IEEE International Electron Devices Meeting (IEDM) (01.12.2015)
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Conference Proceeding
Journal Article
Effects of salt and polyphosphate on physical properties of meat gel treated with microbial transglutaminase
Soeda, T.(Kyushu Kyoritsu Univ., Kitakyushu, Fukuoka (Japan)), Kasagi, T, Hokazono, A, Yamazaki, K, Muguruma, M
Published in Nihon Shokuhin Kagaku Kōgaku kaishi (01.01.2006)
Published in Nihon Shokuhin Kagaku Kōgaku kaishi (01.01.2006)
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Journal Article
Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling
Hokazono, A., Itokawa, H., Mizushima, I., Kawanaka, S., Inaba, S., Toyoshima, Y.
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
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Conference Proceeding
25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)
Hokazono, A, Itokawa, H, Kusunoki, N, Mizushima, I, Inaba, S, Kawanaka, S, Toyoshima, Y
Published in IEEE transactions on electron devices (01.05.2011)
Published in IEEE transactions on electron devices (01.05.2011)
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Journal Article
Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation
Sonehara, T., Hokazono, A., Akutsu, H., Sasaki, T., Uchida, H., Tomita, M., Kawanaka, S., Inaba, S., Toyoshima, Y.
Published in IEEE transactions on electron devices (01.11.2011)
Published in IEEE transactions on electron devices (01.11.2011)
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Journal Article
Scaling strategy for low power RF applications with multi gate oxide Dual Work function (DWF) MOSFETs utilizing self-aligned integration scheme
Miyata, T., Kawanaka, S., Hokazono, A., Ohguro, T., Toyoshima, Y.
Published in 2013 Symposium on VLSI Technology (01.06.2013)
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Published in 2013 Symposium on VLSI Technology (01.06.2013)
Conference Proceeding