FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis
Aziz, Ahsan, Ly, Tai, Kee, Hojin, Mhaske, Swapnil, Spasojevic, Predrag
Published in International Journal of Reconfigurable Computing (01.01.2017)
Published in International Journal of Reconfigurable Computing (01.01.2017)
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Journal Article
High-Throughput FPGA-Based QC-LDPC Decoder Architecture
Mhaske, Swapnil, Hojin Kee, Tai Ly, Aziz, Ahsan, Spasojevic, Predrag
Published in 2015 IEEE 82nd Vehicular Technology Conference (VTC2015-Fall) (01.09.2015)
Published in 2015 IEEE 82nd Vehicular Technology Conference (VTC2015-Fall) (01.09.2015)
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Conference Proceeding
FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques
Hojin Kee, Bhattacharyya, Shuvra S, Wong, Ian, Yong Rao
Published in 2010 IEEE International Conference on Acoustics, Speech and Signal Processing (01.03.2010)
Published in 2010 IEEE International Conference on Acoustics, Speech and Signal Processing (01.03.2010)
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Conference Proceeding
Systematic generation of FPGA-based FFT implementations
Hojin Kee, Petersen, N., Kornerup, J., Bhattacharyya, S.S.
Published in 2008 IEEE International Conference on Acoustics, Speech and Signal Processing (01.03.2008)
Published in 2008 IEEE International Conference on Acoustics, Speech and Signal Processing (01.03.2008)
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Conference Proceeding
Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs
Hsiang-Huang Wu, Hojin Kee, Sane, N, Plishker, W, Bhattacharyya, S S
Published in Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping (01.06.2010)
Published in Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping (01.06.2010)
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Conference Proceeding
A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation
Mhaske, Swapnil, Uliana, David, Hojin Kee, Tai Ly, Aziz, Ahsan, Spasojevic, Predrag
Published in 2015 36th IEEE Sarnoff Symposium (01.09.2015)
Published in 2015 36th IEEE Sarnoff Symposium (01.09.2015)
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Conference Proceeding
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis
Mhaske, Swapnil, Hojin Kee, Tai Ly, Spasojevic, Predrag
Published in 2016 IEEE 37th Sarnoff Symposium (01.09.2016)
Published in 2016 IEEE 37th Sarnoff Symposium (01.09.2016)
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Conference Proceeding
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA
Hojin Kee, Mhaske, Swapnil, Uliana, David, Arnesen, Adam, Petersen, Newton, Riche, Taylor L., Blasig, Dustyn, Tai Ly
Published in 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP) (01.12.2014)
Published in 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP) (01.12.2014)
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Conference Proceeding
Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs
Hojin Kee, Bhattacharyya, S S, Kornerup, J
Published in 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (01.07.2010)
Published in 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (01.07.2010)
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Conference Proceeding
Scalable representation of dataflow graph structures using topological patterns
Sane, N, Hojin Kee, Seetharaman, G, Bhattacharyya, S S
Published in 2010 IEEE Workshop On Signal Processing Systems (01.10.2010)
Published in 2010 IEEE Workshop On Signal Processing Systems (01.10.2010)
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Conference Proceeding
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs
Sane, Nimish, Kee, Hojin, Seetharaman, Gunasekaran, Bhattacharyya, Shuvra S.
Published in Journal of signal processing systems (01.11.2011)
Published in Journal of signal processing systems (01.11.2011)
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Journal Article
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
Kee, Hojin, Shen, Chung-Ching, Bhattacharyya, Shuvra S., Wong, Ian, Rao, Yong, Kornerup, Jacob
Published in Journal of signal processing systems (01.03.2012)
Published in Journal of signal processing systems (01.03.2012)
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Journal Article
Strategies for High-Throughput FPGA-based QC-LDPC Decoder Architecture
Mhaske, Swapnil, Kee, Hojin, Ly, Tai, Aziz, Ahsan, Spasojevic, Predrag
Year of Publication 10.03.2015
Year of Publication 10.03.2015
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Journal Article
PIPELINED LAYERED LDPC DECODING WITH MEMORY ARBITRATION
MHASKE, Swapnil D, AMESEN, Adam T, KEE, Hojin, PETERSEN, Newton G, ULIANA, David C, LY, Tai A
Year of Publication 30.09.2020
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Year of Publication 30.09.2020
Patent
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R
Mhaske, Swapnil, Uliana, David, Kee, Hojin, Ly, Tai, Aziz, Ahsan, Spasojevic, Predrag
Year of Publication 16.05.2015
Year of Publication 16.05.2015
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Journal Article
Self-addressing memory
Kee, Hojin, Arnesen, Adam T, Ly, Tai A, Uliana, David C, Mhaske, Swapnil D, Petersen, Newton G
Year of Publication 25.06.2019
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Year of Publication 25.06.2019
Patent