FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders
Hoe, David H. K., Bollepalli, L. P. Deepthi, Martinez, Chris D.
Published in VLSI Design (01.01.2013)
Published in VLSI Design (01.01.2013)
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Journal Article
Implementing Stochastic Bayesian Inference : Design of the Stochastic Number Generators
Hoe, David H. K., Pajardo, Chet
Published in 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2019)
Published in 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2019)
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Conference Proceeding
Designing stealthy Trojans with sequential logic: A stream cipher case study
Rudra, Mukesh Reddy, Daniel, Nimmy Anna, Nagoorkar, Varun, Hoe, David H. K.
Published in 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2014)
Published in 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2014)
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Conference Proceeding
Stream cipher design using cellular automata implemented on FPGAs
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Conference Proceeding
Optimization of short channel CMOS LNAs by geometric programming
Xiaoyu Jin, Hoe, David H. K.
Published in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2012)
Published in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2012)
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Conference Proceeding
Design and characterization of parallel prefix adders using FPGAs
Hoe, D H K, Martinez, C, Vundavalli, S J
Published in 2011 IEEE 43rd Southeastern Symposium on System Theory (01.03.2011)
Published in 2011 IEEE 43rd Southeastern Symposium on System Theory (01.03.2011)
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Conference Proceeding
Random number generators using Cellular Automata implemented on FPGAs
Comer, J. M., Cerda, J. C., Martinez, C. D., Hoe, D. H. K.
Published in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) (01.03.2012)
Published in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) (01.03.2012)
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Conference Proceeding
An evaluation of CMOS adders in deep submicron processes
Gera, R. J., Hoe, D. H. K.
Published in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) (01.03.2012)
Published in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) (01.03.2012)
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Conference Proceeding
A fault tolerant parallel-prefix adder for VLSI and FPGA design
Martinez, C. D., Bollepalli, L. P. D., Hoe, D. H. K.
Published in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) (01.03.2012)
Published in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) (01.03.2012)
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Conference Proceeding
An efficient FPGA random number generator using LFSRs and cellular automata
Cerda, J. C., Martinez, C. D., Comer, J. M., Hoe, D. H. K.
Published in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2012)
Published in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2012)
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Conference Proceeding
Fault tolerant Block Based Neural Networks
Haridass, Sai sri Krishna, Hoe, David
Published in 2010 42nd Southeastern Symposium on System Theory (SSST) (01.03.2010)
Published in 2010 42nd Southeastern Symposium on System Theory (SSST) (01.03.2010)
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Conference Proceeding
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors
Hoe, David H. K., Rajendran, Jeyavijayan, Karri, Ramesh
Published in 2014 IEEE Computer Society Annual Symposium on VLSI (01.07.2014)
Published in 2014 IEEE Computer Society Annual Symposium on VLSI (01.07.2014)
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Conference Proceeding