Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Lin, Bill, Park, Dongwon
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2021)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2021)
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Journal Article
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes
Lee, Daeyeal, Park, Dongwon, Ho, Chia-Tung, Kang, Ilgweon, Kim, Hayoung, Gao, Sicun, Lin, Bill, Cheng, Chung-Kuan
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2021)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2021)
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Journal Article
InTraSim: Incremental Transient Simulation of Power Grids
Lee, Yu-Min, Ho, Chia-Tung
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.12.2017)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.12.2017)
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Journal Article
Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)
Cheng, Chung-Kuan, Ho, Chia-Tung, Lee, Daeyeal, Lin, Bill
Published in IEEE journal on exploratory solid-state computational devices and circuits (01.06.2021)
Published in IEEE journal on exploratory solid-state computational devices and circuits (01.06.2021)
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Journal Article
Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes
Lee, Daeyeal, Ho, Chia-Tung, Kang, Ilgweon, Gao, Sicun, Lin, Bill, Cheng, Chung-Kuan
Published in IEEE journal on exploratory solid-state computational devices and circuits (01.06.2021)
Published in IEEE journal on exploratory solid-state computational devices and circuits (01.06.2021)
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Journal Article
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop
Ho, Chia-Tung, Kahng, Andrew B.
Published in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2019)
Published in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2019)
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Conference Proceeding
ThermPL: Thermal-aware placement based on thermal contribution and locality
Jiaxing Song, Yu-Min Lee, Chia-Tung Ho
Published in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2016)
Published in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2016)
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Conference Proceeding
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning
Cheng, Chung-Kuan, Ho, Chia-Tung, Holtz, Chester, Lin, Bill
Published in 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) (01.11.2021)
Published in 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) (01.11.2021)
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Conference Proceeding
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization
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Paper
Journal Article
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization
Cheng, Chung-Kuan, Ho, Chia-Tung, Holtz, Chester
Published in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) (17.01.2022)
Published in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) (17.01.2022)
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Conference Proceeding
A Parallel-in-Time Circuit Simulator for Power Delivery Networks with Nonlinear Load Models
Cheng, Chung-Kuan, Ho, Chia-Tung, Jia, Chao, Wang, Xinyuan, Zen, Zhiyu, Zha, Xin
Published in 2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) (01.10.2020)
Published in 2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) (01.10.2020)
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Conference Proceeding
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs
Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng
Published in 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) (01.04.2013)
Published in 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) (01.04.2013)
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Conference Proceeding
Large Language Model (LLM) for Standard Cell Layout Design Optimization
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Conference Proceeding