Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor
Warnock, J., Wendel, D., Aipperspach, T., Behnen, E., Cordes, R.A., Dhong, S.H., Hirairi, K., Murakami, H., Onishi, S., Pham, D.C., Pille, J., Posluszny, S.D., Takahashi, O., Huajun Wen
Published in IEEE journal of solid-state circuits (01.08.2006)
Published in IEEE journal of solid-state circuits (01.08.2006)
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Conference Proceeding
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-Aware Dual Supply Voltage Technique
Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2013)
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Journal Article
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO
Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
Misleading energy and performance claims in sub/near threshold digital systems
Yu Pu, Xin Zhang, Huang, Jim, Muramatsu, Atsushi, Nomura, Masahiro, Hirairi, K, Takata, H, Sakurabayashi, T, Miyano, Shinji, Takamiya, M, Sakurai, T
Published in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2010)
Published in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2010)
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Conference Proceeding
The circuits and physical design of the synergistic processor element of a CELL processor
Takahashi, O., Cook, R., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onishi, S., Pille, J., Silberman, J., Yong, S.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
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Conference Proceeding
The circuit design of the synergistic processor element of a CELL processor
Takahashi, O., Cook, R., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.
Published in ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 (2005)
Published in ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 (2005)
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Conference Proceeding
The circuit design of the synergistic processor element of a CELL processor
Takahashi, O., Cook, R., Cottier, S., Dhong, S. H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.
Published in International Conference on Computer Aided Design: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design; 06-10 Nov. 2005 (31.05.2005)
Published in International Conference on Computer Aided Design: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design; 06-10 Nov. 2005 (31.05.2005)
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0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS
Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y., Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H., Sakurai, T.
Published in 2013 Symposium on VLSI Technology (01.06.2013)
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Published in 2013 Symposium on VLSI Technology (01.06.2013)
Conference Proceeding
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
Yasufuku, T., Iida, S., Fuketa, H., Hirairi, K., Nomura, M., Takamiya, M., Sakurai, T.
Published in IEEE/ACM International Symposium on Low Power Electronics and Design (01.08.2011)
Published in IEEE/ACM International Symposium on Low Power Electronics and Design (01.08.2011)
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Conference Proceeding
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
Flachs, B., Asano, S., Dhong, S. H., Hofstee, H. P., Gervais, G., Kim, R., Le, T., Liu, P., Leenstra, J., Liberty, J. S., Michael, B., Oh, H.-J., Mueller, S. M., Takahashi, O., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Onishi, S., Pille, J., Silberman, J., Yong, S., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D. A., Peyravian, M., To, V., Iwata, E.
Published in IBM journal of research and development (01.09.2007)
Published in IBM journal of research and development (01.09.2007)
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Journal Article
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI : Cell broadband engine technology and systems
FLACHS, B, ASANO, S, MICHAEL, B, OH, H.-J, MUELLER, S. M, TAKAHASHI, O, HIRAIRI, K, KAWASUMI, A, MURAKAMI, H, NORO, H, ONISHI, S, PILLE, J, DHONG, S. H, SILBERMAN, J, YONG, S, HATAKEYAMA, A, WATANABE, Y, YANO, N, BROKENSHIRE, D. A, PEYRAVIAN, M, TO, V, IWATA, E, HOFSTEE, H. P, GERVAIS, G, KIM, R, LE, T, LIU, P, LEENSTRA, J, LIBERTY, J. S
Published in IBM journal of research and development (2007)
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Published in IBM journal of research and development (2007)
Journal Article
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits
Yasufuku, T., Hirairi, K., Yu Pu, Yun Fei Zheng, Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M., Sakurai, T.
Published in Thirteenth International Symposium on Quality Electronic Design (ISQED) (01.03.2012)
Published in Thirteenth International Symposium on Quality Electronic Design (ISQED) (01.03.2012)
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Conference Proceeding
0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS
Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y., Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H., Sakurai, T.
Published in 2013 Symposium on VLSI Circuits (01.06.2013)
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Published in 2013 Symposium on VLSI Circuits (01.06.2013)
Conference Proceeding
The Power Conscious Synergistic Processor Element of a Cell Processor
Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Peter Hofstee, H., Michael, B., Noro, H., Wendel, D., White, M.
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
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