Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology
Hapsari, Emita Yulia, Kumar, Rahul, Sheu, Gene, Shao-Ming Yang, Anil, T. V.
Published in 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) (01.10.2013)
Published in 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) (01.10.2013)
Get full text
Conference Proceeding
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD process technology
Kumar, Ankit, Hapsari, Emita Yulia, Kumar, Vasanth, Mrinal, Aryadeep, Sheu, Gene, Shao-Ming Yang, Ningaraju, Vivek
Published in 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) (01.10.2013)
Published in 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC) (01.10.2013)
Get full text
Conference Proceeding
Optimization of ESD protection device using SCR structure of a novel STI-sided LDMOS with P-top layer for 5 V operating voltage
Hapsari, E. Y., Kumar, A., Vasantha Kumar, V. N., Shao-Ming Yang, Sheu, G.
Published in 2012 International Conference on Optoelectronics and Microelectronics (01.08.2012)
Published in 2012 International Conference on Optoelectronics and Microelectronics (01.08.2012)
Get full text
Conference Proceeding