A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry
Higeta, K., Usami, M., Ohayashi, M., Fujimura, Y., Nishiyama, M., Isomura, S., Yamaguchi, K., Idei, Y., Nambu, H., Ohhata, K., Hanta, N.
Published in IEEE journal of solid-state circuits (01.10.1996)
Published in IEEE journal of solid-state circuits (01.10.1996)
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Journal Article
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry
Higeta, K., Usami, M., Ohayashi, M., Fujimura, Y., Nishiyama, M., Isomura, S., Yamaguchi, K., Idei, Y., Nambu, H., Ohhata, K., Hanta, N.
Published in Proceedings of Bipolar/Bicmos Circuits and Technology Meeting (1995)
Published in Proceedings of Bipolar/Bicmos Circuits and Technology Meeting (1995)
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Conference Proceeding