A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator
Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Shim, Yong, Baek, Kwang-Hyun
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2022)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2022)
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Journal Article
Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems
Seong, Kiho, Jung, Dong-Kyu, Yoon, Dong-Hyun, Han, Jae-Soub, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, Lee, Woojoo, Baek, Kwang-Hyun
Published in Sensors (Basel, Switzerland) (24.04.2020)
Published in Sensors (Basel, Switzerland) (24.04.2020)
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Journal Article
A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator
Han, Jae-Soub, Eom, Tae-Hyeok, Choi, Seong-Wook, Seong, Kiho, Yoon, Dong-Hyun, Kim, Tony Tae-Hyong, Baek, Kwang-Hyun, Shim, Yong
Published in Sensors (Basel, Switzerland) (14.10.2021)
Published in Sensors (Basel, Switzerland) (14.10.2021)
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Journal Article
Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer
Choi, Ji-Min, Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Lee, Woojoo, Baek, Kwang-Hyun
Published in IEEE access (01.01.2020)
Published in IEEE access (01.01.2020)
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Journal Article
A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Chung, Keun-Yong, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2022)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2022)
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Journal Article
A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs
Seong, Kiho, Han, Jae-Soub, Kim, Sung-Eun, Shim, Yong, Baek, Kwang-Hyun
Published in Journal of semiconductor technology and science (31.12.2022)
Published in Journal of semiconductor technology and science (31.12.2022)
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Journal Article
A 3.2-GHz 178-fs rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Chung, Keun-Yong, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2022)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2022)
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Journal Article
A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement
Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Eom, Tae-Hyeok, Han, Jae-Soub, Kim, Ju Eon, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun
Published in 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) (07.11.2021)
Published in 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) (07.11.2021)
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